DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Examiner acknowledges submission of the arguments filed on May 19, 2026. Applicant's arguments have been considered and are sufficient to overcome the previous rejection in view of Huang (US 2009/0168280 A1). A new rejection in view of Liao (US 2023/0138324 A1), Ma (US 2015/0145098 A1), Chen (US 2014/0218829 A1), and Wang (US 2017/0221879 A1) is provided in the current office action, which is made non-final.
Examination Notice
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 9 are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (a)(2) as being anticipated by Liao (US 2023/0138324 A1).
With regard to claim 1, Liao teaches an integrated circuit (100 – Fig. 1), comprising:
a core circuit (112 – Fig. 1, Fig. 11);
a connecting pad (N1 – Fig. 1, Fig. 11);
a high-pass filter (130 – Fig. 1; L1 – Fig. 11) ([0032] lines 1-9) wherein a first terminal (see terminal in Fig. 1 and Fig. 11) of the high-pass filter (130 – Fig. 1; L1 – Fig. 11) is coupled to the connecting pad (N1 – Fig. 1, Fig. 11);
an electrostatic discharge protection circuit (120 – Fig. 1) coupled to the connecting pad (N1 – Fig. 1, Fig. 11) and the first terminal (see terminal in Fig. 1) of the high-pass filter (130 – Fig. 1; L1 – Fig. 11); and
an electrostatic discharge enhanced-protection circuit (116 – Fig. 1; L8 – Fig. 11), wherein a first terminal (GND terminal of 116 – Fig. 1) (also see Fig. 11) of the electrostatic discharge enhanced-protection circuit (116 – Fig. 1; L8 – Fig. 11) is coupled to a second terminal (GND of 130 – Fig. 1) of the high-pass filter (130 – Fig. 1; L1 – Fig. 11), and a second terminal (see second terminal of 116 – Fig. 1 and second terminal L8 – Fig. 11) of the electrostatic discharge enhanced-protection circuit (116 – Fig. 1; L8 – Fig. 11) is coupled to a signal terminal (see signal terminal of 112 – Fig. 1) of the core circuit (112 – Fig. 1).
With regard to claim 9, Liao teaches all the limitations of claim 1, and further teaches a resistor termination network (140 – Fig. 1) coupled to a conductor line (see conductor between N1 and N2 – Fig. 1) connected to the connecting pad (N1 – Fig. 1) and the first terminal of the high-pass filter (130 – Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liao (US 2023/0138324 A1) in view of Ma (US 2015/0145098 A1).
With regard to claim 2, Lia teaches all the limitations of claim 1, but does not teach the core circuit comprises an equalizer, a loss of signal detection circuit or an amplifier.
Ma teaches the core circuit (111 – Fig. 1) comprises an equalizer, a loss of signal detection circuit or an amplifier ([0072] lines 1-6).
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the core circuit of Liao, to have the core circuit comprising an equalizer, a loss of signal detection circuit or an amplifier, as taught by Ma, in order to improve the integrated circuit since this configuration is well known in the art while the amplifier boost the signal strength, the loss of signal (LOS) detection circuit ensures reliability; and the equalizer compensates for signal distortion.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liao (US 2023/0138324 A1) in view of Chen (US 2014/0218829 A1).
With regard to claim 3, Liao teaches all the limitations of claim 1, teaches wherein the high-pass filter (130 – Fig. 1; L1 – Fig. 11) comprises: a capacitor (C1 – Fig. 6) an inductor (L2 – Fig. 6; L1 – Fig. 11). Liao does not teach a capacitor, wherein a first terminal of the capacitor is coupled to the first terminal of the high-pass filter, and a second terminal of the capacitor is coupled to the second terminal of the high-pass filter; and
a resistor, wherein a first terminal of the resistor is coupled to the second terminal of the capacitor, and a second terminal of the resistor is coupled to a reference voltage line.
Chen teaches the high-pass filter (230 – Fig. 2; 320 – Fig. 3) ([0013] lines 5-9, “the high-pass filter 230 may include a capacitor and a transistor or a capacitor and a resistor, or a resistor and an inductor”) comprises:
a capacitor (322 – Fig. 3), wherein a first terminal (upper terminal of 322 – Fig. 3) of the capacitor (322 – Fig. 3) is coupled to the first terminal of the high-pass filter (320 – Fig. 3) (see Fig. 3), and a second terminal (lower terminal of 322 – Fig. 3) of the capacitor (322 – Fig. 3) is coupled to the second terminal (electrical coupled to GND terminal – Fig. 3) of the high-pass filter (320 – Fig. 3); and
a resistor (324 – Fig. 3) ([0017] lines 12-14 “The transistor 324 acts similar to a resistor, affecting the frequency of the signal which passes through the high-pass filter 320 along with the capacitor 322”), wherein a first terminal (upper terminal of 324 – Fig. 3) of the resistor (324 – Fig. 3) is coupled to the second terminal (lower terminal of 322 – Fig. 3) of the capacitor (322 – Fig. 3), and a second terminal (lower terminal of 324 – Fig. 3) of the resistor (324 – Fig. 3) is coupled to a reference voltage line (GND – Fig. 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the high-pass filter of Liao, to have the high-pass filter comprising a capacitor and a resistor, as taught by Chen, in order to lower production costs and because it’s simple design.
Claim(s) 10 are rejected under 35 U.S.C. 103 as being unpatentable over Liao (US 2023/0138324 A1) in view of Wang (US 2017/0221879 A1).
With regard to claim 10, Liao teaches all the limitations of claim 1, but does not teach the resistor termination network comprises:
a switch; and
a resistor, wherein the switch and the resistor are connected in series between the conductor line and a reference voltage line.
Wang teaches the resistor termination network (218 – Fig. 2) comprises:
a switch (M7 – Fig. 2); and
a resistor (R1 – Fig. 2), wherein the switch (M7 – Fig. 2) and the resistor (R1 – Fig. 2) are connected in series between the conductor line (VCC18 – Fig. 2) and a reference voltage line (VSS – Fig. 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the resistor termination network of Liao, to have a switch; and a resistor, wherein the switch and the resistor are connected in series between the conductor line and a reference voltage line as taught by Wang, in order to generate a divided voltage according to the reference voltage, and output the divided voltage to set the bias voltage.
Allowable Subject Matter
Claim(s) 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 4, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a second terminal of the discharge switch is coupled to a reference voltage line, and a control terminal of the discharge switch is controlled by an enable signal of the core circuit, wherein when the enable signal indicates disabling, the discharge switch is turned on, and when the enable signal indicates enabling, the discharge switch is turned off.”
With regard to claim 5, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “the electrostatic discharge enhanced-protection circuit comprises: a transistor, wherein a first terminal of the transistor is coupled to the second terminal of the high-pass filter and the signal terminal of the core circuit, and a second terminal and a control terminal of the transistor are coupled to a reference voltage line.”
With regard to claim 6, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “the electrostatic discharge enhanced-protection circuit comprises: a diode, wherein a cathode of the diode is coupled to the second terminal of the high-pass filter and the signal terminal of the core circuit, and an anode of the diode is coupled to a reference voltage line.”
With regard to claim 7, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a control terminal of the discharge switch is controlled by an enable signal of the core circuit, when the enable signal indicates disabling, the discharge switch is turned on, and when the enable signal indicates enabling, the discharge switch is turned off; and a diode, wherein a cathode of the diode is coupled to the second terminal of the high-pass filter and the signal terminal of the core circuit, and an anode of the diode is coupled to the reference voltage line.”
With regard to claim 8, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a resistor, wherein a first terminal of the resistor is coupled to the first terminal of the electrostatic discharge enhanced-protection circuit, and a second terminal of the resistor is coupled to the second terminal of the electrostatic discharge enhanced-protection circuit; a discharge switch, wherein a first terminal of the discharge switch is coupled to the first terminal of the electrostatic discharge enhanced-protection circuit, a second terminal of the discharge switch is coupled to a reference voltage line, a control terminal of the discharge switch is controlled by an enable signal of the core circuit, when the enable signal indicates disabling, the discharge switch is turned on, and when the enable signal indicates enabling, the discharge switch is turned off; and a transistor, wherein a first terminal of the transistor is coupled to the second terminal of the electrostatic discharge enhanced-protection circuit, and a second terminal and a control terminal of the transistor are coupled to the reference voltage line.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached PTO-892.
Yeh (US 11,862,960 B2) teaches an ESD protection circuit includes a first diode, a second diode and an ESD clamp circuit, an RC network wherein Resistor R1 and capacitor C1 are configured as the RC network. Dependent upon a location of an output of the RC network, the RC network is configured as either a low pass filter or a high pass filter.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas Bellido whose telephone number is (571) 272-5034. The examiner can normally be reached Monday to Friday from 9:00 am to 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/N.B./Examiner, Art Unit 2838
/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
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