DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 05/22/2024 is considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “plurality of switching circuit units, coupled to the…plurality of basic circuit units of the semiconductor circuit” of Claim 1 and “a plurality of switching circuit units is coupled to the plurality of basic circuit units” of Claim 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 16, 17, 19, 20 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Pereira et al. (US 20200191849), hereinafter ‘Pereira’.
Regarding Claims 1 and 16, Pereira disclsoes a correction system, configured to correct a semiconductor circuit (Fig. 5, 500 integrated circuit; Para [0011] reducing noise on a semiconductor circuit according to one embodiment includes providing at least one circuit node on the semiconductor circuit; Para [0044] IC 500 implemented with a system and method of duplicate circuit block swapping for noise reduction), and comprising: a plurality of redundant circuit units, coupled to the semiconductor circuit (Fig. 5, duplicate comparators 510 and 512 integrated on IC 500; Para [0046] the comparator circuit block of the oscillator is duplicated); a plurality of switching circuit units, coupled to the plurality of redundant circuit units (Para [0045] Select terminal 51 of the first MUX 522 is coupled to the negative input of the first comparator 510, select terminal S2 of the first MUX 522 is coupled to the negative input of the second comparator 512; Fig. 5 MUX 522 and appears second MUX 522 should be MUX 524 per Para [0045] node 111 (VT) is coupled to the D terminal of a second analog MUX 524) and a plurality of basic circuit units of the semiconductor circuit (Para [0036] there are a number N of duplicate blocks integrated onto a IC in close proximity to each other, in which N is any suitable integer number greater than one (e.g., 2, 3, 4, 8, 16, etc.), if one of the circuit blocks is affected with RTN, then chances are that the remaining circuit blocks are not); and a control circuit, coupled to the semiconductor circuit and the plurality of switching circuit units(Fig. 5, 108; Para [0032] an output coupled to a node 115 developing a clock signal CLK. CLK is provided to an input of the switching logic 108, which has a set of control outputs controlling the switches; nodes 111 and 113, respectively, coupled to MUX 522/524 thru 526, coupled to node 115 which is then coupled to switch control 108), configured to obtain a noise signal of the semiconductor circuit, configured to determine whether the semiconductor circuit passes a noise test by recognizing a characteristic of the noise signal (Para [0044] 500 implemented with a system and method of duplicate circuit block swapping for noise reduction; Para [0047]; Fig. 6), and configured to replace one of the plurality of basic circuit units with one of the plurality of redundant circuit units (Abstrct a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices) by controlling the plurality of switching circuit units when the semiconductor circuit does not pass the noise test (Para [0045-0046] duplicate comparators 510 and 512 are integrated in close proximity to each other within a circuit area 503 of the IC 500. It is assumed for purposes of illustration that the comparator 510 (or comparator A) is affected by RTN and comparator 512 (or comparator B) is not; The MUXes 522, 524, and 526 and the DFF 528 collectively form a switch circuit 520 for alternatively coupling one the comparators 510 and 512 (or comparators A and B, respectively) with each falling edge of CLK. When SEL is high, the comparator A is coupled into the oscillator 501 and comparator B is disconnected, and when SEL is low, comparator A is disconnected and comparator B is coupled into the oscillator 501. When a selected one of the comparators A and B is coupled into the oscillator 501, node 113 (VREF) is coupled to the negative input, node 111 (VT) is coupled to the positive input, and node 115 (CLK) is coupled to the output of the selected comparator. SEL is toggled to opposite states with each falling edge of CLK. In this manner, rather than duplicating and swapping the entire oscillator circuit block, only the comparator circuit block of the oscillator is duplicated and swapped in successive cycles of CLK).
Regarding Claims 2 and 17, Pereira further discloses wherein the control circuit is further configured to obtain another noise signal of the semiconductor circuit when the semiconductor circuit is operated with the one of the plurality of redundant circuit units and others of the plurality of basic circuit units, and is configured to determine whether the semiconductor circuit passes the noise test by recognizing a characteristic of the another noise signal (Abstrct a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices; Para [0048] Operation repeats in this manner for the 13.sup.th and 14.sup.th cycles. When VT discharges down to TL1 at the end of the 14.sup.th cycle, however, the RTN is no longer active so that when the comparator A is next selected for the 15.sup.th cycle, VT charges to TH1 and back down to TL1 according to normal operation. Operation continues in this manner while the RTN is not active for the remaining cycles up to the 31.sup.st cycle at the EOC.).
Regarding Claims 4 and 19, Pereira further discloses wherein the control circuit is further configured to determine that the semiconductor circuit does not pass the noise test when the characteristic of the noise signal comprises a characteristic of random telegraph noise (Para [0001] system and method of sequentially replacing or swapping duplicate circuit blocks to reduce Random Telegraph Noise (RTN) or “popcorn” noise in an electronic circuit; Para [0045] comparator 510 (or comparator A) affected by RTN).
Regarding Claims 5 and 20, Pereira further discloses wherein the control circuit is further configured to determine that the semiconductor circuit passes the noise test when the characteristic of the noise signal does not comprise the characteristic of random telegraph noise (Para [0001] system and method of sequentially replacing or swapping duplicate circuit blocks to reduce Random Telegraph Noise (RTN) or “popcorn” noise in an electronic circuit; Para [0045] comparator 512 (or comparator B) not affected by RTN).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 6, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pereira et al. (US 20200191849), hereinafter ‘Pereira’ as applied to claims 1 and 16 above, and further in view of Meller et al. (US 20140269867), hereinafter ‘Meller’.
Regarding Claims 3, 6 and 18, Pereira discloses the system according to claims 1 and 16 above. Pereira fails to disclose wherein the noise signal is obtained by the control circuit when the semiconductor circuit is operated with the plurality of basic circuit units and wherein the control circuit is further configured to receive and process a signal of the semiconductor circuit to obtain the noise signal.
Meller discloses burst triggered signal analysis wherein a number of separate burst noise events can be determined by a controller, processor, or other logic over a period of time (Para [0027]). Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide the noise signal to be obtained by the control circuit when the semiconductor circuit is operated with the plurality of basic circuit units and wherein the control circuit is further configured to receive and process a signal of the semiconductor circuit to obtain the noise signal for the benefit determining and reducing external factors which exacerbate parameters of signals as taught by Meller in Para [0027, 0002].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pereira et al. (US 20200191849), hereinafter ‘Pereira’.
Regarding Claim 15, Pereira discloses the claimed invention except for the wherein an amount of the plurality of redundant circuit units is less than an amount of the plurality of basic circuit units, and an amount of the plurality of switching circuit units is equal to a sum of the amount of the plurality of redundant circuit units and the amount of the plurality of basic circuit units. It would have been obvious to one with ordinary skill in the art at the time of the invention, to experiment with various amounts of redundant circuits and basic circuit units, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Benis Co., 193 USPQ 8.
Allowable Subject Matter
Claims 7-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the closest prior art fails to disclose nor would it be obvious to combine “wherein the semiconductor circuit comprises a first stage circuit and an output stage circuit, an output terminal of the first stage circuit is coupled to an input terminal of the output stage circuit, an output terminal of the output stage circuit is coupled to an inverting input terminal of the first stage circuit, and the plurality of switching circuit units, the plurality of basic circuit units and the plurality of redundant circuit units are all arranged on the first stage circuit” in combination with all limitations of the claim and base claims. All subsequent claims would also be allowable due to dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALESA ALLGOOD whose telephone number is (571)270-5811. The examiner can normally be reached M-F 7:30 AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALESA ALLGOOD/Primary Examiner, Art Unit 2858