DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 05/23/2024. Claims 1-20 are pending in the Application, of which Claims 1 and 12 are independent.
Continuity/ Priority Information
The present Application 18672020 filed 05/23/2024 Claims Priority from Provisional Application 63506828, filed 06/07/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/02/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noda (Pub. No. US 20030165112) Pub. Date: 2003-09-04.
Regarding independent Claims 1 and 12, Noda discloses a communication system and a communication method employing multi-level modulation system, comprising:
a demodulator configured to demodulate the received channel codes to obtain a demodulated data vector; Referring to FIG. 1, [0099] In the receiving apparatus 121, the six-phase demodulator 122 performs six-phase demodulation of the received signal 138 which has been sent from the transmitting apparatus 101 over the transmission line and received by the receiving apparatus 121, and outputs a ternary received sequence 139 and a binary received sequence 140.
a syndrome computer configured to compute a data vector syndrome for the demodulated data vector; The ternary received sequence 139 is supplied to the syndrome calculation circuit 123. The syndrome calculation circuit 123 constitutes part of a ternary error correction decoding circuit associated with the ternary error correction encoding circuit 103, and generates a syndrome 141 from the ternary received sequence 139.
a controller configured to receive the data vector syndrome …..store a plurality of pre-computed test error pattern syndromes; receive the search key from the controller; concurrently evaluate the plurality of test error pattern syndromes under a codebook membership criterion with the search key; The low-order digit correction circuit 128 uses the syndrome 141 and the parity difference 145 to correct an error in the ternary received sequence 139, and then supplies a ternary decoded sequence 147 to the 6-ary to binary conversion circuit 130. The high-order digit correction circuit 129 corrects an error in the delayed binary received sequence 144 based on a ternary received sequence 146-1 and a ternary decoded sequence 146-2 supplied from the low-order digit correction circuit 128, thereby generating a binary decoded sequence 148 for supply to the 6-ary to binary conversion circuit 130. The 6-ary to binary conversion circuit 130 converts the received ternary decoded sequence 147 and the binary decoded sequence 148 into a received binary signal 149 to output the received binary signal 149.
determine an address of a candidate test error pattern corresponding to a candidate test error pattern syndrome that satisfy the codebook membership criterion; and a word-generation module configured to: use the determined address to retrieve indices of non-zero elements of the candidate test error pattern; and generate a candidate output codeword based on the retrieved indices of non-zero elements of the test error pattern and the input data vector.
[0165] Referring to FIG. 18, the ternary error correction decoding circuit 153 includes among others, an error location calculating unit 153-2 to “determine an address” [0166] The syndrome calculating unit 153-1 computes the syndrome of a ternary received sequence 139. The error location-calculating unit 153-2 generates an error locator polynomial, from the syndrome, and solves the error locator polynomial to compute an error location. The error value-calculating unit 153-3 is supplied with the syndrome and with the error location and computes an error value from the error locator polynomial and a derivative of the error locator polynomial. The error pattern-generating unit 153-4 generates an error pattern from the error location and from the error value. The delay circuit 153-6 delays the ternary received signal sequence a preset time. The error pattern subtraction unit 153-6 subtracts the error pattern from the delayed ternary received signal sequence to output a ternary decoded sequence 141.
Regarding Claims 2, 3, 13,14, Noda discloses wherein the demodulator configured to demodulate the received channel codes on basis of a hard-decision algorithm to obtain a hard-decided vector, wherein the demodulator is configured to demodulate the received channel codes on basis of a soft-decision algorithm to obtain a soft-decided vector; Referring to FIG. 1 [0099] In the receiving apparatus 121, the six-phase demodulator 122 performs six-phase demodulation of the received signal 138 which has been sent from the transmitting apparatus 101 over the transmission line and received by the receiving apparatus 121. Referring to FIG.18, [0166] The syndrome calculating unit 153-1 computes the syndrome of a ternary received sequence 139. The error location-calculating unit 153-2 generates an error locator polynomial, from the syndrome, and solves the error locator polynomial to compute an error location. The error value-calculating unit 153-3 is supplied with the syndrome and with the error location and computes an error value from the error locator polynomial and a derivative of the error locator polynomial.
Regarding Claims 4, 5, 15, 16, Noda discloses wherein the reliability order is an ascending order of absolute values of the individual elements of the soft-decided vector, and wherein the controller is further configured to calculate a likelihood value for each of the one or more candidate output codewords based on the corresponding demodulated data vector. [0100] First, the code parameters of the ternary BCH (Bose-Chaudhuri-Hocquenghem) code as typical of the ternary error correction code will be explained. The ternary BCH code is formed on the basis of the following p-degree generating polynomial p(x) having coefficients of a.sub.0,a.sub.1, . . . a.sub.p with the elements of 0, 1, 2: p(x)=x.sup.p+a.sub.p 1x.sup.p-1+ . . . +a.sub.1x+a.sub.0 (1) [0101] where [0102] a.sub.i=0,1,2.
Regarding Claims 6-11, 17-20, Noda discloses wherein the plurality of test error pattern syndromes is ranked into the one or more subsets according to the Hamming weights of the corresponding TEPs thereof; and the compute-in-memory comprises one or more sub-memories, each configured to: store a corresponding subset of test error pattern syndromes; and evaluate the corresponding subset of test error pattern syndromes with the codebook membership criterion based on the channel codeword syndrome.
Referring to FIG. 18, [0166] The syndrome calculating unit 153-1 computes the syndrome of a ternary received sequence 139. The error location-calculating unit 153-2 generates an error locator polynomial, from the syndrome, and solves the error locator polynomial to compute an error location. The error value-calculating unit 153-3 is supplied with the syndrome and with the error location and computes an error value from the error locator polynomial and a derivative of the error locator polynomial. The error pattern-generating unit 153-4 generates an error pattern from the error location and from the error value. The delay circuit 153-6 delays the ternary received signal sequence a preset time. The error pattern subtraction unit 153-6 subtracts the error pattern from the delayed ternary received signal sequence to output a ternary decoded sequence 141. Meanwhile, a ternary received sequence 139-1 and a ternary decoded sequence 139-2 are sent to the high order digit correction circuit 129.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 20080148129 Moon; Jaekyun et al. Error detection and correction using error pattern correcting codes
US 5930272 Thesling; William H. Block decoding with soft output information
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: June 11, 2026
Non-Final Rejection 20260611
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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