Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/672,140 filed on May 23, 2024.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Device Comprising Trench Gate Structure With Heterogeneous Epitaxial Buffer Layer in a Semiconductor Layer”.
Claim Objections
6. Claim 4 is objected to because of the following informalities: In the following, the claim should be recited to avoid indefiniteness due to lack of antecedent basis, and/or perform proper alignment of the claim languages:
4. (Currently amended) The semiconductor device according to claim 1, wherein a first part, a second part and a third part of the body region are sequentially adjoining along a width direction of the trench gate structure,
the first part and the second part of the body region are located between two trench gate structures, the first part adjoins the first sidewall of the trench, the second part is close to a second sidewall of the trench, the first surface is opposite to the second surface,
the third part and the second part are close to the same trench, the third part is located between a bottom surface of the trench and the second surface, and the third part and the first part are isolated by the drift region,
wherein the second part adjoins the second sidewall, or the second part and the second part are isolated by the drift region.
Appropriate correction is needed.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
10. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 1, 3-5, 9, 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Grasse et al. (US 2020/0144370 A1) in view of Sheng et al. (US 2023/0130726 A1).
Regarding independent claim 1, Grasse et al. teaches a semiconductor device (500, para [0082]), comprising (Fig. 2B) a semiconductor layer (100, para [0082]), a trench gate structure (150 trench gate stripe, para [0082]), wherein the semiconductor layer (100) has a first surface (upper surface) and a second surface (bottom surface) opposite each other, the trench gate structure (150) is at least partially located in a trench (see the annotated figure below) on the first surface (upper surface) of the semiconductor layer (100),
the semiconductor layer (100) comprises:
a source region (110, para [0066]) extending from the first surface (upper surface) toward the second surface (bottom surface);
a drift region (131, para [0083]) and a body region (140), wherein at least a part of the drift region (131) is located between the body region (140) and the second surface (bottom surface) of the semiconductor layer (100),
wherein a first part (see the annotated figure below) of the body region (140) is located between the source region (110) and the drift region (131) along a direction of the first surface (upper surface) to the second surface (bottom surface), the first part of the body region (140) and the source region (110) both adjoin a first sidewall of the trench,
the source region (110) and the drift region (131) are of a first conductivity type (n-type), the body region (140) is of a second conductivity type (p-type), and the first conductivity type is opposite to the second conductivity type.
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Grasse et al. is silent to explicitly disclose a buffer layer, wherein the buffer layer is a heterogeneous epitaxial layer of the semiconductor layer and covers an inner surface of the trench and the first surface of the semiconductor layer, the buffer layer is located between a gate dielectric layer of the trench gate structure and the semiconductor layer.
Sheng et al. discloses wherein (Fig. 16), a buffer layer (1302, para [0054]), wherein the buffer layer (1302) is a heterogeneous epitaxial layer (para [0054]) of the semiconductor layer and covers an inner surface of the trench and the first surface of the semiconductor layer, the buffer layer (1302) is located between a gate dielectric layer (see in figure below) of the trench gate structure (see the figure below) and the semiconductor layer.
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Sheng et al. and incorporate the epitaxial protection region in the semiconductor structure of Grasse et al., in order to effectively reduce the electric field of the gate dielectric, and can play a better role in suppressing the short circuit of the device at the same time (para [0054]).
Regarding claim 3, Grasse et al. and Sheng et al. teach all of the limitations of claim 1 from which this claim depends.
Sheng et al. discloses wherein (Fig. 16), a thickness of the buffer layer (1302) comprises a thickness of one or more atomic layers (1302 comprises more atomic layers because of larger thickness).
Regarding claim 4, Grasse et al. and Sheng et al. teach all of the limitations of claim 1 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), a first part (see the annotated figure below), a second part (see the annotated figure below) and a third part (see the annotated figure below) of the body region (140) are sequentially adjoining along a width direction of the trench gate structure (150),
the first part and the second part of the body region are located between two trench gate structures (150 left and right), the first part adjoins the first sidewall of the trench, the second part is close to a second sidewall of the trench, the first surface is opposite to the second surface,
the third part and the second part are close to the same trench, the third part is located between a bottom surface of the trench and the second surface, and the third part and the first part are isolated by the drift region (131),
wherein the second part adjoins the second sidewall, or the second part and the second part are isolated by the drift region (131).
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Regarding claim 5, Grasse et al. and Sheng et al. teach all of the limitations of claim 4 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), the third part (see the annotated figure in claim 4) of the body region (140) extends from the bottom surface of the trench toward the second surface; or
at least part of the bottom surface is separated from the third part of the body region by the drift region along the direction of the first surface to the second surface.
Regarding claim 9, Grasse et al. and Sheng et al. teach all of the limitations of claim 4 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), edges of the second part (see figure in claim 4) and the third part (see figure in claim 4) of the body region (140) facing toward the second surface (bottom surface) are connected; or
an edge of the third part (see figure in claim 4) facing toward the second surface (bottom surface) is closer to the second surface than an edge of the second part facing toward the second surface (bottom surface).
Regarding claim 14, Grasse et al. and Sheng et al. teach all of the limitations of claim 1 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), the semiconductor layer (100) further comprises a body contact region (170) extending from the first surface toward the second surface, and the body contact region (170) adjoins the body region (140),
the body contact region (170) adjoins the source region (110), or is separated from the source region by the body region,
wherein the body contact region (170) is of the second conductivity type (n+).
Regarding claim 15, Grasse et al. and Sheng et al. teach all of the limitations of claim 14 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), along an extension direction of the trench gate structure (150), a part of the body contact region (170) adjoins the second sidewall, another part of the body contact region (170) has a space from the second sidewall, and the part of the body contact region (170) adjoining the second sidewall and the part of the body contact (170) having the space from the second sidewall are arranged alternatively along the extension direction of the trench gate structure (150), or
the body contact region is separated from the second surface by the body region.
Regarding claim 16, Grasse et al. and Sheng et al. teach all of the limitations of claim 1 from which this claim depends.
The combination of Grasse et al. and Sheng et al. teaches wherein, the trench gate structure (150, Fig. 2B, Grasse et al.) comprises the gate dielectric layer (159, para [0061]) and a gate conductor (155, para [0061]),
the gate dielectric layer (159) covers the buffer layer (1302, Fig. 16, Sheng et al.) on the inner surface (bottom inner surface) of the trench and covers part (upper part) of buffer layer (1302) on first surface adjacent to the trench, the trench extending from the first surface (upper surface) toward the second surface (bottom surface),
a part of the gate conductor (155) is in the trench, another part extends outside the trench and covers the gate dielectric layer (159),
wherein the gate dielectric layer (159) is located between the gate conductor (155) and the buffer layer (1302, Fig. 16 modified by Sheng et al.), so as to separate the gate conductor (155) and the buffer layer (1302).
Regarding claim 17, Grasse et al. and Sheng et al. teach all of the limitations of claim 1 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), the semiconductor device (500) is a metal-oxide semiconductor field effect transistor (para [0082]) or an insulated gate bipolar transistor.
Regarding claim 18, Grasse et al. and Sheng et al. teach all of the limitations of claim 4 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), between two trench gate structures (150 left and right), the source region (110) extends from the first sidewall of one trench towards the second sidewall of the other trench, and adjoins the second part of the body region (140).
12. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Grasse et al. (US 2020/0144370 A1) in view of Sheng et al. (US 2023/0130726 A1) as applied to claim 1 above, and further in view of Loechelt et al. (US 2018/0012994 A1).
Regarding claim 2, Grasse et al. and Sheng et al. teach all of the limitations of claim 1 from which this claim depends.
Grasse et al. teaches wherein (Fig. 2B), the semiconductor layer (100) comprises a silicon carbide (para [0055]) semiconductor layer.
Grasse et al. and Sheng et al. are silent to explicitly disclose wherein the buffer layer comprises one or more of a Si layer, a SiGe layer, a GaN layer and a GaAs layer.
Loechelt et al. discloses wherein (Fig. 3C), the buffer layer (304, para [0037]) comprises one or more of a Si layer (para [0037]), a SiGe layer, a GaN layer and a GaAs layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Sheng et al. and modify the buffer material of Grasse et al. and Sheng et al. with silicon material, in order to reduce mutual counter-doping (para [0037]).
Allowable Subject Matter
13. Claims 6 (claims 7-8, 13 depend on the claim 6), and 10 (claims 11-12 depend on the claim 10) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6: the prior art of record alone or in combination neither teaches nor makes obvious the semiconductor device comprising:
Claim 6 recites …. the second part of the body region comprises a first sub-region and a second sub-region that are connected,
along the direction of the trench gate structure, the first sub-region adjoins the first part of the body region, the second sub-region adjoins the third part of the body region,
wherein, a distance from an edge of the first part of the body region facing toward the second surface to the first surface is a first distance, a distance from an edge of the first sub-region facing toward the second surface to the first surface is a second distance, a distance from an edge of the second sub-region facing toward the second surface to the first surface is a third distance,
the third distance is greater than the second distance, and the second distance is greater than the first distance.
Claim 10: the prior art of record alone or in combination neither teaches nor makes obvious the semiconductor device comprising:
Claim 10 recites ….the semiconductor layer further comprises a channel drain region, located between the first part of the body region and the drift region, so that the source region, the first part of the body region and the channel drain region are sequentially adjoining in a direction of the first surface to the second surface and adjoin a first sidewall of the trench,
the channel drain region adjoins the drift region and the second part of the body region, respectively, and the channel drain region is separated from the third part of the body region by the drift region,
wherein the channel drain region is of the first conductivity type.
The prior arts, Grasse et al. (US 2020/0144370 A1), Sheng et al. (US 2023/0130726 A1) and/or Loechelt et al. (US 2018/0012994 A1) does not disclose the limitations stated in the section 12 above, therefore, either by itself or in combination with other arts fail to disclose the quoted limitations.
Examiner’s Note
14. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
16. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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