DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 14 and the corresponding claims 1-7 and 11-20 in the reply filed on 07/20/2026 is acknowledged.
Claim 8-10 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/20/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/23/2024 and 03/24/2025 was filed after the mailing date of the application on 05/23/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, US 20230146151 A1 (Lee).
Regarding claim 1; Lee teaches a semiconductor device comprising:
a first gate structure (Lee: First Version of annotated Fig (41) shared in this OA: First Gate Structure; 330) in a cell region (First Version of annotated Fig (39) shared in this OA: Cell Region; it is worth noting that Figures (39)-(41) are cross sectional perspectives along the lines A-A’, B-B’, C-C’ and D-D’ of Fig (35), respectively, and thus they appear to represent the same embodiment.) of a substrate (105),
wherein the substrate (105) comprises a peripheral circuit region (Peripheral Circuit Region);
a bit line structure (Fig (39): 247+257+267+277; [0051]: “A dummy bit line structure including a seventh conductive pattern 247, a fourth barrier pattern 257, an eighth conductive pattern 267 and a second mask 277 sequentially stacked”) on the cell region of the substrate (105);
a cell capacitor structure (670+680+690; [0108]: “Each of the plurality of first lower electrodes 660 and portions of the first dielectric pattern 670, the first upper electrode 680 and the third upper electrode 690 may be referred as a first capacitor 700”) on the bit line structure (247+257+267+277);
a decoupling capacitor structure (705; [0010]: “…The second capacitor structure including a plurality of second capacitors 705 on a pair of first conductive pads 605 on the second region II of the substrate 100 may form a decoupling capacitor.”) on the peripheral circuit region (Peripheral Circuit Region) of the substrate (105); and
a second gate structure (Second Gate Structure; 330) on the decoupling capacitor structure (705).
PNG
media_image1.png
645
1182
media_image1.png
Greyscale
PNG
media_image2.png
741
1089
media_image2.png
Greyscale
Regarding claim 2; Lee discloses all the limitations of the semiconductor device according to claim 1.
Lee teaches further comprising a plurality of second gate structures (Lee: First Version of annotated Fig (41) shared in this OA: Plurality of Second Gate Structures) comprising the second gate structure (Second Gate Structure), wherein the plurality of the second gate structures (Plurality of Second Gate Structures) are spaced apart from each other on the peripheral circuit region (Peripheral Circuit Region) of the substrate (105) in a horizontal direction (D1) that is substantially parallel to an upper surface of the substrate (105).
Regarding claim 3; Lee teaches all the limitations of the semiconductor device according to claim 1.
Lee teaches further comprising a third gate structure (Lee: First Version of annotated Fig (39) shared in this OA: 170) on the cell capacitor structure (670+680+690).
Regarding claim 4; Lee teaches all the limitations of the semiconductor device according to claim 1
Lee teaches further comprising a plurality of decoupling capacitor structures (Lee: First Version of annotated Fig (41) shared in this OA: Plurality of Decoupling Capacitor Structures) comprising the decoupling capacitor structure (705), wherein the plurality of the decoupling capacitors (Plurality of Decoupling Capacitor Structures) are spaced apart from each other on the peripheral circuit region (Peripheral Circuit Region) of the substrate (105) in a horizontal direction (D1) that is substantially parallel to an upper surface of the substrate (105).
Regarding claim 5; Lee teaches all the limitations of the semiconductor device according to claim 1.
Lee teaches further comprising a third gate structure (Lee: First Version of annotated Fig (41) shared in this OA: Third Gate Structure) on the peripheral circuit region (Peripheral Circuit Region) of the substrate, wherein the third gate structure (Third Gate Structure) is spaced apart from the decoupling capacitor structure (705).
Regarding claim 6; Lee teaches all the limitations of the semiconductor device according to claim 1.
Lee teaches wherein the decoupling capacitor structure (Lee: First Version of annotated Fig (41) shared in this OA: 705) comprises: first capacitor electrodes (665) that are spaced apart from each other in a horizontal direction (D1) that is substantially parallel to an upper surface of the substrate (105), wherein each of the first capacitor electrodes (665) extends in a vertical direction (D3) that is substantially perpendicular to the upper surface of the substrate (105); a dielectric pattern (675) on upper and side surfaces of the first capacitor electrodes (665); a second capacitor electrode (685) on the dielectric pattern (675); and a third capacitor electrode (695) on the second capacitor electrode (685).
Regarding claim 7; Lee teaches all the limitations of the semiconductor device according to claim 6
Lee teaches further comprising a conductive pad (Lee: First Version of annotated Fig (41) shared in this OA: 605) that is electrically connected to lower surfaces of the first capacitor electrodes (665).
Regarding claim 11; Lee teaches all the limitations of the semiconductor device according to claim 1.
Lee teaches wherein the decoupling capacitor structure (Lee: First Version of annotated Fig (39) shared in this OA: 705) and the cell capacitor structure (670+680+690) are separated from an upper surface of the substrate (105) by a substantially same distance (T1; T2).
Regarding claim 12; Lee teaches a semiconductor device comprising:
a first gate structure (Lee: Annotated Fig (41) shared in this OA: First Gate Structure; 330) in a cell region (Cell Region) of a first substrate (Second Version of annotated Fig (39) shared in this OA: 590; it is worth noting that Figures (39)-(41) are cross sectional perspectives along the lines A-A’, B-B’, C-C’ and D-D’ of Fig (35), respectively, and thus they appear to represent the same embodiment.),
wherein the first substrate (590) comprises a peripheral circuit region (Peripheral Region);
a bit line structure (247+257+267+277) on the cell region (Cell Region) of the first substrate (590);
a cell capacitor (670+680+690; [0108]: “Each of the plurality of first lower electrodes 660 and portions of the first dielectric pattern 670, the first upper electrode 680 and the third upper electrode 690 may be referred as a first capacitor 700”) on the bit line structure (247+257+267+277);
a decoupling capacitor structure (705; [0010]: “…The second capacitor structure including a plurality of second capacitors 705 on a pair of first conductive pads 605 on the second region II of the substrate 100 may form a decoupling capacitor.”) at least partially in the peripheral circuit region (Peripheral Circuit Region) of the first substrate (590); and
a second gate structure (170) on the peripheral circuit region (Peripheral Circuit Region) of the first substrate (590),
wherein the second gate structure (170) is a first distance (T3) from an upper surface of the first substrate (590),
wherein the cell capacitor structure (670+680+690) is a second distance (T4) from the upper surface of the first substrate (590), and wherein the first distance (T3) is greater than the second distance (T4).
PNG
media_image3.png
756
1126
media_image3.png
Greyscale
Regarding claim 13; Lee teaches all the limitations of the semiconductor device according to claim 12.
Lee teaches further comprising a plurality of second gate structures (Lee: Second version of annotated Fig (39) shared in this OA: Second Gate Structures) comprising the second gate structure (170), wherein the plurality of the second gate structures (Second Gate Structures) are spaced apart from each other on the peripheral circuit region (Peripheral Circuit Region) of the first substrate (590) in a horizontal direction (D1) that is substantially parallel to the upper surface of the first substrate (590).
Regarding claim 14; Lee teaches all the limitations of the semiconductor device according to claim 12.
Lee teaches further comprising a third gate structure (Lee: First version of Fir (41) shared in this OA: Third Gate Structure) on the cell capacitor structure (670+680+690).
Regarding claim 15; Lee teaches all the limitations of the semiconductor device according to claim 12.
Lee teaches further comprising a second substrate (Lee: Second version of Fig (39) shared in this OA: 105) on the first substrate (590), wherein a lower surface of the second substrate (105) is on the second gate structure (170).
Regarding claim 16; Lee teaches all the limitations of the semiconductor device according to claim 12.
Lee teaches further comprising a second substrate(Lee: Second version of Fig (39) shared in this OA: 105) on the first substrate (590), wherein the second gate structure (170) is on an upper surface of the second substrate (105).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Alzate-Vinasco et al, US 20220415896 A1 (Alzate-Vinasco) in view of Lee, US 20230146151 A1 (Lee).
Regarding claim 17; Alzate-Vinasco teaches a semiconductor device (Alzate-Vinasco: Annotated Fig (1A) shared in this OA: 100A) comprising:
a first substrate (180) comprising a first cell region (First Cell Region) and a first peripheral circuit region (First Peripheral Circuit Region);
a first gate structure (102A+102B) in the first cell region (First Cell Region) of the first substrate (180);
a bit line structure on the first cell region (First Cell Region) of the first substrate (180);
a cell capacitor (106) structure on the bit line structure;
a decoupling capacitor structure (110) on the first peripheral circuit region (First Peripheral Circuit Region) of the first substrate (180);
a second substrate (183) on the cell capacitor structure (106) and the decoupling capacitor structure (110),
wherein the second substrate (183) comprises a second cell region (Second Cell Region) and a second peripheral circuit region (Second Peripheral Circuit Region) that correspond to the first cell region (First Cell Region) of the first substrate (183) and the first peripheral circuit region (First Peripheral Circuit Region) of the first substrate (180), respectively;
a second gate structure (104A+104B) on the second cell region (Second Cell Region) of the second substrate (183);
a third gate structure on the second peripheral circuit region (Second Peripheral Circuit Region) of the second substrate (183); and
through vias (140; 116) that extend into the second substrate (183),
wherein ones of the through vias (140; 116) are electrically connected to the cell capacitor structure (106; [0054]:” As shown, top portions or surfaces of each of the electrodes 106B and 108B are coupled together by a top conductive plate 138 extending laterally above each of the electrodes 106B and 108B. The top conductive plate 138 extends on level 115, and laterally over to an interconnect 140 in region 101A. Top conductive plate 138 serves a substantially same purpose as top conductive plate 114.”) and the decoupling capacitor structure (110; [0049]: “As shown, top portions or surfaces of each of the electrodes 110B and 112B are coupled together by a top conductive plate 114 extending laterally above each of the electrodes 110B and 112C. The top conductive plate 114 extends on a level 115, above level 109, and laterally extends over to an interconnect 116. In the illustrative embodiment, interconnect 116 is a via and the top conductive plate 114 divides the via into two vertical portions. The two vertical portions may or may not be of equal size.”).
PNG
media_image4.png
665
889
media_image4.png
Greyscale
Alzate-Vinasco does not teach a bit line structure on the first cell region.
However, Lee teaches a bit line structure (Lee: Annotated Fig (39) shared in this OA: 247+257+267+277) on the first cell region (Cell Region).
Alzate-Vinasco and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Alate-Vinasco by constructing a bit line in the cell region as disclosed in Lee to improve the ability of addressing of the individual cells leading to a more reliable device.
Alzate-Vinasco does not teach a third gate structure on the second peripheral circuit region.
Lee teaches a third gate structure (Lee: Second Version of annotated Fig (41) shared in this OA: Third Gate Structure) on the second peripheral circuit region (Peripheral Circuit Region).
Alzate-Vinasco and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Alate-Vinasco by constructing a third gate structure in the peripheral circuit region as disclosed in Lee to improve the control of individual cells leading to a more reliable device.
PNG
media_image5.png
645
1184
media_image5.png
Greyscale
Regarding claim 18; Alzate-Vinasco in view of Lee teaches all the limitations of the semiconductor device according to claim 17.
Alzate-Vinasco does not teach further comprising a plurality of third gate structures comprising the third gate structure, wherein the plurality of the third gate structures are spaced apart from each other on the second peripheral circuit region of the second substrate in a horizontal direction that is substantially parallel to an upper surface of the second substrate.
Lee teaches further comprising a plurality of third gate structures (Lee: Second version of annotated Fig (41) shared in this OA: Plurality of Third Gate Structures) comprising the third gate structure (Third Gate Structure), wherein the plurality of the third gate structures (Plurality of Third Gate Structures) are spaced apart from each other on the second peripheral circuit region (Peripheral Circuit Region) of the second substrate (380) in a horizontal direction (D1) that is substantially parallel to an upper surface of the second substrate (380).
Alzate-Vinasco and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Alate-Vinasco by constructing the plurality of third gate structures as disclosed in Lee to improve control over the current flowing in the cell thus leading to a more reliable device.
Regarding claim 19; Alzate-Vinasco in view of Lee teach all the limitations of the semiconductor device according to claim 17.
Alzate-Vinasco does not teach further comprising a plurality of decoupling capacitor structures comprising the decoupling capacitor structure, wherein the plurality of the decoupling capacitor structures are spaced apart from each other on the first peripheral circuit region of the first substrate in a horizontal direction substantially parallel to an upper surface of the first substrate.
Lee teaches further comprising a plurality of decoupling capacitor structures (Lee: Second version of annotated Fig (41) shared in this OA: Plurality of Decoupling Capacitor Structures) comprising the decoupling capacitor structure (705), wherein the plurality of the decoupling capacitor structures (Plurality of Decoupling Capacitor Structures) are spaced apart from each other on the first peripheral circuit region(Peripheral Circuit Region) of the first substrate (105) in a horizontal direction substantially (D1) parallel to an upper surface of the first substrate (105).
Alzate-Vinasco and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Alzate-Vinasco by constructing a plurality of decoupling capacitor structures as disclosed in Lee to improve the isolation of the cell from electronic noise in other parts of the device thus leading to a more reliable device.
Regarding claim 20; Alzate-Vinasco in view of Lee teaches all the limitations of the semiconductor device according to claim 17.
Alzate-Vinasco does not teach further comprising a fourth gate structure on the first peripheral circuit region of the first substrate, wherein the fourth gate structure is spaced apart from the decoupling capacitor structure.
Lee teaches further comprising a fourth gate structure (Lee: Second version of annotated Fig (41) shared in this OA: Fourth Gate Structure) on the first peripheral circuit region (Peripheral Circuit Region) of the first substrate (105), wherein the fourth gate structure (Fourth Gate Structure) is spaced apart from the decoupling capacitor structure (705).
Alzate-Vinasco and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Alzate-Vinasco by constructing a fourth gate structure as disclosed in Lee to improve control over the current flowing in the circuit and thus improve the performance of the circuit.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Jeon et al, US 20240186247 A1 (Jeon); discloses trench decoupling capacitors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
