DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office Action is in response to Applicant’s amendment filed on February 27, 2026. Claims 1, 7-8, 11, 14, 16 and 19 have been amended. No new claims have been added. Claim 3 has been canceled. Currently claims 1-2 and 4-20 are pending.
Response to Arguments
Applicant's arguments with respect to claims 1, filed on February 27, 2026 have been fully considered but they are not persuasive. The reason is set forth below.
Regarding Amended claims 1, the applicant stated “It can be seen that, in BANG, the gate electrode G1 of the first transistor T1 is not electrically connected to an active semiconductor layer. As is well known to those skilled in the art, the active semiconductor layer specifically refers to the semiconductor layer for forming a channel and controlled by the gate electrode, which does not include a drain region. That is, the semiconductor layer of BANG cannot be regarded as the active semiconductor layer of this application.
Therefore, Applicant respectfully submits that BANG does not disclose the feature "a drive gate of the drive transistor is electrically connected to the active semiconductor layer through a drive via hole" as recited in amended claim 1.
Further, the Office Action cited the lines SLk and SLk+1 shown in Fig. 3 of BANG to comment on the above features. However, Fig. 3 of BANG merely shows that the lines SLk and SLk+1 are located at the upper and lower sides of PX(k,p), respectively, and does not illustrate an overlap between the PX(k,p) and the lines SLk and SLk+1. Further, the description corresponding to Fig. 3 of BANG also does not disclose that there is an overlap between the PX(k,p) and the lines SLk and SLk+1. That is, BANG does not disclose the feature "wherein the first subpixel is overlapped with at least two signal lines, and the at least two signal lines are disposed on both sides of a center of the first subpixel, respectively" of amended claim 1.”
However, the primary reference BANG (US 20190280076 A1) "BANG et al." ¶ [0090] clearly discloses “The gate electrode G1 of the first transistor T1 is electrically connected to the drain region D4 of the fourth transistor T4 via a connection electrode 153.” D4 is a drain region and drain regions are doped, therefore active region. Furthermore, when the channel is active connected to the source and drain regions. Therefore, when the drain is connected to the gate region via the connection electrode, in an Active state it is also connected to the channel region.
Furthermore, BANG et al. Figs. 1-5, 10-11 and ¶ [0045] to [0047] discloses “The plurality of scan lines SL1 to SLn is arranged in rows, and each scan line transfers a scan signal. As shown in FIG. 2, in an exemplary embodiment, the scan lines connected to each pixel include a first scan line 131 that applies a first scan signal GI, a second scan line 133 that applies a second scan signal GW, and a third scan line 135 that applies a third scan signal GB.” and “The plurality of scan lines SL1 to SLn and the plurality of data lines DL11 to DL2m are arranged as a matrix, and the pixels PX are arranged at cross-sections thereof. The pixels PX may include first pixels, second pixels, and third pixels that emit light of different colors from one another. For example, in an exemplary embodiment, the first pixel is a red pixel R that emits red light, the second pixel is a blue pixel B that emits blue light, and the third pixel is a green pixel G that emits green light. The first, second, and third pixels may be arranged according to a predetermined rule. For example, in an exemplary embodiment, the first and second pixels may be arranged alternately in a column, and the third pixels may be arranged in a column adjacent to the column in which the first and second pixels are arranged.”
Therefore, Primary Reference BANG (US 20190280076 A1) "BANG et al." discloses all the limitations cited in Amended Claims 1. For the stated reasons above a final rejection has been made using BANG (US 20190280076 A1) "BANG et al." in view of (US 20210027717 A1) "KIM et al.".
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1-2 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over BANG (US 20190280076 A1) “BANG et al.” in view of (US 20210027717 A1) “KIM et al.”.
Regarding Independent Claim 1, BANG et al. Figs 1-8 discloses a display substrate (Fig 1. “A display apparatus 10”, ¶ [0042]), comprising:
multiple subpixels (“a pixel portion 100”, ¶ [0043], “a plurality of pixels PX” ¶ [0044]), wherein at least one of the multiple subpixels comprises a pixel circuit (“FIG. 2 is an equivalent circuit diagram of a pixel PX” ¶ [0053]) and a light-emitting element (“a light-emitting device connected to the pixel circuit” ¶ [0054]) that are on a base substrate 110, and the pixel circuit comprises a drive transistor (“The first transistor T1 acts as a driving transistor” ¶ [0057]), configured to drive the light-emitting element to emit light (“receives a data signal to supply an electric current to the organic light-emitting diode OLED according to a switching operation of the second transistor T2.” ¶ [0057]);
an active semiconductor layer (“a semiconductor layer” ¶ [0079]), wherein a drive active layer (“T1 includes a gate electrode G1 connected to a lower electrode Cst1 of the capacitor Cst” ¶ [0057]) of the drive transistor T1 is in the active semiconductor layer (“the semiconductor layers of the first to seventh transistors T1 to T7” ¶ [0085]), and a drive gate (“gate electrodes G1 to G7” ¶ [0085]) of the drive transistor T1 is electrically connected to the active semiconductor layer (“a connection electrode 153” ¶ [0090]) through a drive via hole CH1 (“a contact hole CH1” ¶ [0090]; and
a first conducting layer (“the first data line 161 (DL1), the second data line 161 (DL2), and the connection electrode 163 are arranged on the fourth insulating layer 115.” ¶ [0109]), on a side of the active semiconductor layer away from the base substrate 110, wherein the first conducting layer comprises anode adapter portions 163 (“the connection electrode 163” ¶ [0109]) and signal lines 161 (DL1) & 161 (DL2) (“the first data line 161 (DL1), the second data line 161 (DL2)” ¶ [0109]) that are disposed at intervals (Fig. 6); and
a first insulation layer (Fig. 5, “insulating layer 116” ¶ [0097]), on a side of the first conducting layer 161 away from the base substrate 10, wherein the first insulation layer comprises first via holes, and the first via holes expose at least a part of the anode adapter portions 163 (“contacts the connection electrode 163 via the second via VIA2.” ¶ [0097]);
wherein in each of the subpixels PX, an orthographic projection of at least a part of the drive via hole (“The connection electrode 153 is disposed on a third insulating layer 114, and may respectively contact the gate electrode G1 of the first transistor T1 and the drain region D4 of the fourth transistor T4 via a contact hole CH1 and a contact hole CH2. The contact hole CH1 is disposed in a second insulating layer 113 and the third insulating layer 114, and partially exposes the gate electrode G1 of the first transistor T1.” ¶ [0090]) on the base substrate 110 does not overlap (Fig. 4 shows orthogonal projections of the contact hole CHI, the connecting electrode 163, and the data line 161 on the substrate do not overlap) orthographic projections of an anode adapter portion 163 and signal lines 161 (DL1) & 161 (DL2) on the base substrate 110.
the light-emitting element (“organic light-emitting diode OLED” ¶ [0097]) comprises an anode (“electrode 310” ¶ [0097]), the anode 310 is on a side of the first insulation layer 116 away from the base substrate 110, and a layer where the anode is located and the first conducting layer have an overlapping region (Fig. 5 shows 310 and 163 has overlapping regions);
the multiple subpixels comprise first subpixels and second subpixels (“The pixels PX may include first pixels, second pixels” ¶ [0047])
wherein the first subpixel is overlapped with at least two signal lines, and the at least two signal lines are disposed on both sides of a center of the first subpixel, respectively (Fig. 3 shows first pixel overlap with two signal line SLk and SLk+1).
However, BANG et al. does not disclose sizes of the first subpixels in a first direction are greater than sizes of the second subpixels in the first direction.
In the similar field of endeavor of display devices KIM et al. Fig. 3 discloses sizes of the first subpixels in a first direction are greater than sizes of the second subpixels in the first direction (“third color pixel PX3 may be smaller than the light-emitting region EMA of each first color pixel PX1” ¶ [0063]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the pixel sizes of BANG et al. with the pixel sizes of KIM et al. in order to improve visibility (or display quality) (KIM et al. ¶ [0165]).
Regarding Claim 2, BANG et al. as modified by KIM et al. discloses the limitations of claim 1. BANG et al. Figs. 1-4 further discloses wherein a signal line corresponding to the second subpixel is at a side of a center of the second subpixel (“The plurality of scan lines SL1 to SLn is arranged in rows, and each scan line transfers a scan signal. As shown in FIG. 2, in an exemplary embodiment, the scan lines connected to each pixel” ¶ [0045]), and an anode adapter portion 163 (“” ¶ [0114]) corresponding to the second subpixel is at the other side of the center of the second subpixel (Fig. 4 scan line 133 and anode adapter 163 is located in two different sides).
With Regard to Claim 20, BANG Figs 1-8 discloses a display apparatus (Fig 1. “A display apparatus 10”, ¶ [0042]), comprising the display substrate according to claim 1.
Allowable Subject Matter
Claim 4-19, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With Regard to Claim 4, closest the prior art of record, (US 20190280076 A1) “BANG et al.” and (US 20210027717 A1) “KIM et al.”. alone or in combination does not teach or fairly suggest, in each of the first subpixels, an orthographic projection of the anode adapter portion on the base substrate does not overlap an orthographic projection of the drive active layer on the base substrate, and an orthographic projection of the main body portion on the base substrate does not overlap the orthographic projection of the anode adapter portion on the base substrate; and in each of the second subpixels, an orthographic projection of the anode adapter portion on the base substrate overlaps an orthographic projection of the drive active layer on the base substrate, and an orthographic projection of the main body portion on the base substrate overlaps the orthographic projection of the anode adapter portion on the base substrate, in combination with other limitations of claim 1.
With Regard to Claim 5-19 are indicated allowable based on its dependency on claim 4.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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