Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated March 2, 2026, claims 1-19 and 21 are active in
this application.
Claim Objections
Claims 2-6 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7-9 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vergis et al. [US Patent Application # 20160350002].
With respect to claim 1, Vergis et al. disclose a memory system, comprising: a command/address channel [C/A BUS 112 – FIG. 1]; a first memory die [0000 120] coupled with the command/address channel and comprising a first circuit ["an on-chip or on-die controller that is included on the memory devices 120" - par. 0031] configured to output a first identifier of the first memory die ["In one embodiment, system 100 assigns a unique ID to each memory device..." – par. 0035 (The assignment and storage of a unique DID (Device ID) directly implies that the device "outputs" or stores its specific ID.)] to a first register configured to store the first identifier ["memory devices 120 includes a register... can store DID information in an MPR (multipurpose register), mode register, or other register." – par. 0035 (the patent discloses storing the ID (DID) in a register (MPR/Mode Register) on the device.)]; and a second memory die [0001 120] coupled with the command/address channel and comprising a second circuit ["an on-chip or on-die controller that is included on the memory devices 120" - par. 0031] configured to output a second identifier of the second memory die ["In one embodiment, system 100 assigns a unique ID to each memory device..." – par. 0035 (The assignment and storage of a unique DID (Device ID) directly implies that the device "outputs" or stores its specific ID.)] to a second register configured to store the second identifier["memory devices 120 includes a register... can store DID information in an MPR (multipurpose register), mode register, or other register." – par. 0035 (the patent discloses storing the ID (DID) in a register (MPR/Mode Register) on the device.); and, "In such a mode, only the memory device with matching ID will exit self-refresh, and the others will ignore the command..." – par. 0035 (This functionality necessitates that each device stores its own specific ID in its own internal register (1st and 2nd register).)] .
With respect to claim 7, Vergis et al. disclose a first voltage source coupled with the second circuit of the second memory die; and a second voltage source coupled with the first circuit of the first memory die [“RCD 110 issues read and/or write commands to the selected memory device 120 to execute the data transfer for the data access operation. In response to a detection of power failure, the operations will primarily be read operations to read data from memory devices 120 to write to storage. When power is restored, the operations may be primarily write operations to restore the data from storage to memory devices 120. – par. 0040 (the text describes functional individual die control (via per-device self-refresh))].
With respect to claim 8, Vergis et al. disclose the first memory die and the second memory die are coupled with a host system and are accessible by a peripheral system coupled with the host system via an interface [“RCD 110 is a registered clock driver (which can also be referred to as a registering clock driver). The registered clock driver receives information from the host (such as a memory controller) and buffers the signals from the host to the various memory devices 120. “ – par. 0031].
With respect to claim 9, Vergis et al. disclose the first memory die and the second memory die are coupled with a peripheral system and are accessible by a host system via an interface [“RCD 110 is a registered clock driver (which can also be referred to as a registering clock driver). The registered clock driver receives information from the host (such as a memory controller) and buffers the signals from the host to the various memory devices 120. “ – par. 0031].
With respect to claim 21, Vergis et al. disclose the first identifier is based on a first set of values of a first set of signals; and the second identifier is based on a second set of values of a second set of signals [“memory devices 120 coupled to port B of RCD 110, coupled to data bus 114B could be numbered from 0000:0111, similar to memory devices 120 of data bus 114A. As long as each memory device 120 on a common command and address bus or control line, and data bus has a unique ID assigned to it, the system can generate device specific self-refresh commands. With the 4 bit IDs illustrated, there are 16 possible unique IDs, which is one example, and more or fewer bits can be used to address each device, depending on the implementation.” – par. 0030].
Allowable Subject Matter
Claims 11-19 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2: The memory system of claim 1, wherein the first circuit comprises: a first pull-down circuit coupled with a first node of the first circuit; a first latch coupled with the first node and configured to output the first identifier; and an inverter coupled with the first node.
-with respect to claim 10: The memory system of claim 1, wherein: the first identifier comprises an indication that the first memory die is an interface die, and the second identifier comprises an indication that the second memory die is a linked die.
-with respect to claim 11, store, at the register, a first identifier of the first location based at least in part on detecting the first location; detect, by the second circuit of the second memory die, a second location of the second memory die relative to the first memory die; and store, at the register, a second identifier of the second location based at least in part on detecting the second location.
-with respect to claim 18, storing, at a first register associated with the first memory die, a first identifier of the first location based at least in part on detecting the first location; detecting, by a second circuit of the second memory die, a second location of the second memory die relative to the first memory die; and storing, at a second register associated with the second memory die, a second identifier of the second location based at least in part on detecting the second location.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 March 20, 2026