DETAILED ACTION
This action is responsive to the election received on 08/19/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, Species A, and Species C in the reply filed on 08/19/2026 is acknowledged. The traversal is on the ground(s) that there is no search burden on the examiner. This is not found persuasive because the applicant is required to specifically point out the reason(s) on which they base their conclusion(s) that a requirement to restrict is in error. A mere broad allegation that the identified mutually exclusive species are “similar” does not clearly show that there is no search burden on the examiner. Applicant has not stated on the record that they believe the identified mutually exclusive species are obvious variants or provided evidence showing this to be the case. The requirement is still deemed proper and is therefore made FINAL.
Claim(s) 15-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/23/2026.
Claim(s) 7-9 and 13 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/23/2026.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application(s) filed in REPUBLIC OF KOREA on 10/05/2023 and 11/03/2023.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/23/2024 and 06/10/2024 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitations “a horizontal width of ones of the plurality of posts is greater than . . .” in line 3 followed by “a horizontal width of ones of the plurality of posts is smaller than . . .” in line 5 such that there are two recitations of “a horizontal width of ones of the plurality of posts” and it is unclear if these two horizontal widths are representing the same horizontal width (i.e. the second recitation should be “the horizontal width”) or two different horizontal widths (i.e. the second recitation should be “a second horizontal width”) since any three-dimensional structure may have a plurality of widths. Therefore, since the antecedent basis is unclear, claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 5-6 are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, claim 4 will be interpreted to read as “a horizontal width of ones of the plurality of posts is greater than a horizontal width of the metal layer, a second horizontal width of ones of the plurality of posts is smaller than a horizontal width of the upper pads”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 10-12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0371726 A1; Liao et al.; 12/2019; (“Liao”).
Regarding Claim 1. Liao discloses A semiconductor package (#1000a, Figure 29), comprising:
a first redistribution structure including upper pads (#120, Figure 29, conductive pads);
a semiconductor chip (#300, Figure 29, semiconductor component) on the first redistribution structure (Figure 29, #300 is on #120 where “on” does not require direct contact);
an encapsulant (#PM’, #220’, #UF, #160’, #140a, and #130a, Figure 29, polished dielectric layer, encapsulant, underfill, protection layer, post-passivation layer, and passivation layer which all comprise dielectric materials and together encapsulate a plurality of structures, referred to in the following as “ENCAP”) on the first redistribution structure and surrounding the semiconductor chip (Figure 29, ENCAP are on #120 and at least partially surround #300);
a second redistribution structure (#RDL2’, Figure 29, redistribution structure) on the encapsulant (Figure 29, #RDL2’ is on ENCAP) and including an upper redistribution layer (#250a, Figure 29, #250a of #RDL2’ is a conductive line which may be interpreted as an upper redistribution layer);
a plurality of posts (#TVs and underlying #RWs and #CVs, Figure 29, through vias, redistribution wirings, and conductive vias, referred to as “POST” in the following) penetrating the encapsulant (Figure 29, POST penetrates ENCAP) and electrically connecting the upper pads of the first redistribution structure to the upper redistribution layer of the second redistribution structure (Figure 29, POST forms an electrical connection between #120s and #250a of #RDL2’);
a metal layer (#150, Figure 29, conductive pillar) between the upper pads and the plurality of posts (Figure 29, #150s are electrically and physically between #120s and POST) and having an upper surface having a first step difference with an upper surface of an edge of the upper pads (Figure 29, #150 has an upper surface which has a first lateral step difference with an upper surface of #120 as it is narrower than #120); and
a seed layer (#S’, Figure 29, patterned seed layer) between the metal layer and the plurality of posts (Figure 29, #S’ is electrically and physically between #150 and POST).
Regarding Claim 2. Liao discloses The semiconductor package of claim 1, wherein a horizontal width of ones of the plurality of posts is greater than a horizontal width of the metal layer (Figure 29, a horizontal width of at least #TV in POST is greater than a horizontal width of #150).
Regarding Claim 3. Liao discloses The semiconductor package of claim 1, wherein a horizontal width of the upper surface of an edge of the upper pads is 2 µm or more and 4 µm or less (Figure 29, since the bounds of “an edge” have not been defined by the claim, a horizontal width of an upper surface of #120 may be set from the leftmost or rightmost edge towards the center at a distance of 2-4 µm as necessary and defined as upper surface of an edge of the upper pads since the total width of #120 is at least 2 µm based on [0027] and Figure 9).
Regarding Claim 4. Liao discloses The semiconductor package of claim 1, wherein
a horizontal width of ones of the plurality of posts is greater than a horizontal width of the metal layer (Figure 29, a horizontal width of at least #TV in POST is greater than a horizontal width of #150),
a second horizontal width of ones of the plurality of posts is smaller than a horizontal width of the upper pads (Figure 29, horizontal width of #CV in POST is smaller than horizontal width of #120), and
at least a portion of a lower surface of the plurality of posts is exposed to oppose at least a portion of the upper surface of an edge of the upper pad (Figure 29, at least a portion of a lower surface of #RW of POST is exposed to oppose an edge of the upper surface of #120).
Regarding Claim 5. Liao discloses The semiconductor package of claim 1, wherein
the lower surface of the plurality of posts, a side surface of the metal layer, and the upper surface of an edge of the upper pad define a first recessed portion recessed in a direction toward a center of the metal layer when viewed in a cross-sectional view (Figure 29, a lower surface of #RW of POST, a side surface of #150, and an upper surface of an edge of #120 define a recessed portion in a direction toward a center of #150), and
at least a portion of the encapsulant is in the first recessed portion (Figure 29, at least a portion f #PM’ of ENCAP is located in the above defined recessed portion).
Regarding Claim 6. Liao discloses The semiconductor package of claim 5, wherein the encapsulant contacts the lower surface of an edge of the plurality of posts in the first recessed portion (Figure 29, ENCAP contacts the lower surface of an edge of #RW of POST in the above defined recessed portion).
Regarding Claim 10. Liao discloses A semiconductor package (#1000a, Figure 29), comprising:
a first redistribution structure including upper pads (#120, Figure 29, conductive pads);
a semiconductor chip (#300, Figure 29, semiconductor component) on the first redistribution structure (Figure 29, #300 is on #120 where “on” does not require direct contact);
an encapsulant (#PM’, #220’, #UF, #160’, #140a, and #130a, Figure 29, polished dielectric layer, encapsulant, underfill, protection layer, post-passivation layer, and passivation layer which all comprise dielectric materials and together encapsulate a plurality of structures, referred to in the following as “ENCAP”) on the first redistribution structure and surrounding the semiconductor chip (Figure 29, ENCAP are on #120 and at least partially surround #300);
a second redistribution structure (#RDL2’, Figure 29, redistribution structure) on the encapsulant (Figure 29, #RDL2’ is on ENCAP) and including an upper redistribution layer (#250a, Figure 29, #250a of #RDL2’ is a conductive line which may be interpreted as an upper redistribution layer);
a plurality of posts (#TVs and underlying #RWs and #CVs, Figure 29, through vias, redistribution wirings, and conductive vias, referred to as “POST” in the following) penetrating the encapsulant (Figure 29, POST penetrates ENCAP) and electrically connecting the upper pads of the first redistribution structure to the upper redistribution layer of the second redistribution structure (Figure 29, POST forms an electrical connection between #120s and #250a of #RDL2’); and
a metal layer (#150, Figure 29, conductive pillar) between the upper pads and the plurality of posts (Figure 29, #150s are electrically and physically between #120s and POST) and exposing an upper surface of an edge of the upper pads and a lower surface of an edge of the plurality of posts (Figure 29, at least a portion of a lower surface of #RW of POST is exposed to oppose an edge of the upper surface of #120).
Regarding Claim 11. Liao discloses The semiconductor package of claim 10, wherein,
a side surface of the plurality of posts protrudes further than a side surface of the metal layer when viewed in a cross-sectional view (Figure 29, a side surface of POST protrudes further than a side surface of #150 when viewed in the cross-sectional view),
the semiconductor package defines a first groove portion recessed in a direction toward a center of the metal layer along a side surface of the metal layer between the plurality of posts and the upper pads (Figure 29, a lower surface of #RW of POST, a side surface of #150, and an upper surface of an edge of #120 define a recessed portion in a direction toward a center of #150), and
the encapsulant is in the first groove portion (Figure 29, at least a portion f #PM’ of ENCAP is located in the above defined recessed portion).
Regarding Claim 12. Liao discloses The semiconductor package of claim 11, wherein the encapsulant has a portion below the plurality of posts in the first groove portion (Figure 29, ENCAP has a portion below POST in the above defined first groove/recessed portion).
Regarding Claim 14. Liao discloses A method of manufacturing a semiconductor package (#1000a, Figures 1-29), the method comprising:
forming a first redistribution structure including an upper pad (#120, Figure 1, conductive pads) having a first width (Figure 1, #120s have a width);
forming a metal layer (#150, Figure 22, conductive pillar) on the upper pad (Figure 2, #150 is formed on #120), the metal layer having a second width smaller than the first width (Figure 2, #150s have a width which is smaller than the width of #120);
forming a post (#TVs and underlying #RWs and #CVs, Figures 2-26, through vias, redistribution wirings, and conductive vias, referred to as “POST” in the following) on the metal layer (Figure 26, POST is on #150), the post having a width greater than the second width (Figure 26, at least the #TV of POST has a width which is greater than the width of #150);
forming a semiconductor chip (#300, Figure 24, semiconductor component) on the first redistribution structure (Figure 24, #300 is on #120), the semiconductor chip electrically connected to at least a portion of the upper pad (Figure 24, #300 is electrically connected to at least a portion of #120 through the underlying structure similar to POST);
forming an encapsulant (#PM’, #220’, #UF, #160’, #140a, and #130a, Figure 26, polished dielectric layer, encapsulant, underfill, protection layer, post-passivation layer, and passivation layer which all comprise dielectric materials and together encapsulate a plurality of structures, referred to in the following as “ENCAP”) on the first redistribution structure (Figure 26, ENCAP is on #120), the encapsulant at least partially surrounding the semiconductor chip and the post (Figure 26, ENCAP at least partially surrounds POST and #300); and
forming a second redistribution structure (#RDL2’, Figure 29, redistribution structure) on the encapsulant (Figure 29, RDL2’ is on ENCAP).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0087999 A1; Wang et al.; 03/2024 – Figures 3 and 4A disclose a packaging substrate structure wherein the width of the conductive post (#100) narrows in the region of the underlying conductive pad (#102) such that “a post pitch between neighboring conductive posts not being limited by a minimum lateral separation distance between the respective conductive pads” (see [0007]).
US 2024/0363464 A1; Tai et al.; 03/2024 – Figure 1I disclose a packaging substrate structure wherein the width of the conductive post (#27) including a seed layer (#22a) narrows in the region of the underlying conductive pad (#17a) of a redistribution layer.
US 2021/0057347 A1; Liu et al.; 02/2021 – Figures 1U and 2A disclose a packaging substrate structure wherein the width of the conductive post (#100) including a narrower seed layer (#402) narrows in the region of the underlying conductive pad structure (#414) of a redistribution layer to form a groove filled by an encapsulant (#408).
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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