CTNF 18/672,372 CTNF 84369 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 and 5-12 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by US 9899305 (Yeh et al) . Concerning claim 1, Yeh discloses a semiconductor package comprising (Figs. 1, 3, and 4, note that Fig. 1 is used to identify the parts of the semiconductor structure of Fig. 3) : a substrate (20) that comprises a first surface (201) and a second surface (202) that is opposite to the first surface (Fig. 3) , wherein the first surface comprises a first region (Fig. 4 region of 30a) and a second region (Fig. 4 region of 30b) , wherein the first region is adjacent to a first side of the substrate (Fig. 4) , wherein the second region is adjacent to a second side of the substrate (Fig. 4) , wherein the first side and the second side are opposite to each other, and wherein the substrate comprises a wiring circuit layer (col. 3 lines 33-37) ; first connection pads (73) in the first region of the substrate and second connection pads (73) in the second region of the substrate, wherein the first connection pads and the second connection pads are electrically connected to the wiring circuit layer (col. 3 lines 33-37) ; a semiconductor chip structure (30a) that is on the first region of the substrate and is connected to the first connection pads by conductive bumps (65) (col. 4 lines 3-10) ; a stiffener (2) that extends along the first side and is in the first region of the substrate (Fig. 4) , wherein the stiffener extends to both corners of the first side (Fig. 4) ; an underfill (74) on the first region of the substrate, wherein the underfill is spaced apart from the stiffener (Fig. 3 and col. 4 lines 3-10) , wherein the underfill at least partially surrounds the conductive bumps (Fig. 3) , and wherein the underfill is between the semiconductor chip structure and the substrate (Fig. 3) ; and external connection conductors (60) that are on the second surface of the substrate and electrically connected to the wiring circuit layer (Fig. 3) . Continuing to claim 5, Yeh discloses wherein the stiffener comprises a metal material (col. 4 lines 51-54). Considering claim 6, Yeh discloses wherein the stiffener comprises at least one of stainless steel, copper (Cu), copper (Cu) alloy, nickel (Ni), or a nickel (Ni) alloy (col. 4 lines 51-54) . Regarding claim 7, Yeh discloses wherein a height in which the stiffener extends from the first surface of the substrate is less than a height in which the semiconductor chip structure extends from the first surface of the substrate (Fig. 3). Referring to claim 8, Yeh discloses wherein the semiconductor chip structure comprises a package that comprises a redistribution substrate (70) , a redistribution layer (35) , and a semiconductor chip (47) (col. 3 lines 60-67) . Pertaining to claim 9, Yeh discloses wherein the semiconductor chip structure comprises a plurality of semiconductor chips (30a and 30b) that are on the first surface of the substrate and that extend in a direction that is perpendicular to the first surface (Figs. 3 and 4). Considering claim 10, Yeh discloses wherein the semiconductor chip structure comprises at least one logic chip (col. 3 lines 44-56). Continuing to claim 11, Yeh discloses further comprising a memory chip structure that is in the second region of the substrate and comprises a memory chip (col. 3 lines 44-56). Concerning claim 12, Yeh discloses wherein the stiffener extends along a perimeter of the semiconductor chip structure and a perimeter of the memory chip structure (Fig. 4) . 07-15-aia AIA Claim(s) 13-16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by US 20140048326 (Lin et al) . As to claim 13, Lin discloses a semiconductor package comprising (Figs. 3A-8 and 10) : a substrate (201) ; a semiconductor chip structure (61+62) that is on the substrate and adjacent to one side surface of the substrate (Figs. 3A and Fig. 10) ; a stiffener (31 +313) that overlaps at least two corner portions of an upper surface of the substrate in a first direction (Fig. 3A) , wherein the stiffener is spaced apart from the semiconductor chip structure (Fig. 10) , and wherein the stiffener comprises a tetragonal shape that at least partially surrounds the semiconductor chip structure (Fig. 3A) ; and an underfill (91) that overlaps at least a portion of a lower end of the semiconductor chip structure in the first direction (Fig. 10). Concerning claim 14, Lin discloses wherein a first region defined by an internal side surface of the stiffener is larger than a second region defined by the semiconductor chip structure (Fig. 3A) . Continuing to claim 15, Lin discloses wherein the underfill is connected to at least a portion of the stiffener (Fig. 10, note that the underfill is connected to the substrate 201 which is connected to the stiffener and therefore the underfill is connected to the stiffener by way of the substrate) . Regarding claim 16, Lin discloses wherein the stiffener extends along an external edge of the upper surface of the substrate (Fig. 3A) 07-15-aia AIA Claim(s) 17, 18, and 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by US 20220068756 (Jang et al) . Pertaining to claim 17, Jang discloses a semiconductor package comprising (Figs. 2 and 13) : a substrate (100) ; a first semiconductor chip structure (310) and a second semiconductor chip structure (320) that are on an upper surface of the substrate and comprise different sizes (Figs. 2 and 13) ; a stiffener (500) that is spaced apart from the first semiconductor chip structure and the second semiconductor chip structure and is on the upper surface of the substrate (Fig. 2) , wherein the stiffener extends along a perimeter of the first semiconductor chip structure and a perimeter of the second semiconductor chip structure (Fig. 13) ; and an underfill (260) that seals at least a portion of the first semiconductor chip structure and at least a portion of the second semiconductor chip structure ([0038]) , wherein the first semiconductor chip structure and the second semiconductor chip structure comprise a plurality of semiconductor chips that extend in a direction that is perpendicular to the upper surface of the substrate (Fig. 13) . As to claim 18, Jang discloses wherein the plurality of semiconductor chips are a plurality of logic chips (Fig. 13 and [0040]). Concerning claim 20, Jang discloses wherein the stiffener is a metal film layer ([0032]) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9899305 (Yeh et al) as applied to claim 1 above, and further in view of US 20140048326 (Lin et al) . Continuing to claims 2 and 3, Yeh discloses wherein the stiffener further comprises a portion that extends . . . in a direction that is perpendicular to the first side (Fig. 4) and wherein the stiffener further comprises a first portion that extends along the second side. Yeh does not disclose that the stiffener extends from the both corners of the first side or a first portion . . . extends to both corners of the second side. However, Lin discloses a stiffener configuration in which first and second portions of the stiffener extend from all corners of the substrate (Fig. 3A). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See MPEP 2144.04 IV B. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the stiffener configuration in view of Lin absent evidence that the claimed configuration is significant. Considering claim 4, Yeh in view of Lin discloses wherein the stiffener further comprises a second portion that extends parallel to the first side and the second side (Yeh Fig. 4 and Lin Fig. 3A) . 07-22-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220068756 (Jang et al) as applied to claim 17 above, and further in view of US 20150200186 (Park) . Regarding claim 10, Jang discloses forming the semiconductor chip structure with a plurality of logic chips (Figs. 2 and 13). Jang does not disclose wherein the plurality of logic chips comprise a lower logic chip that comprises a through-electrode and an upper logic chip that is electrically connected to the substrate through the through-electrode. However, Park discloses a semiconductor package configuration (Fig. 15) that includes a stiffener structure (400) ([0077]) that surrounds a semiconductor structure configuration that includes a lower logic chip that comprises a through-electrode and an upper logic chip that is electrically connected to the substrate through the through-electrode ([0020]-[0025]). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See MPEP 2144.04 IV B. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, considering both devices are logic chips, to modify the logic chip configuration in view of Park absent evidence that the claimed configuration is significant . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 11302592 discloses a semiconductor package having a stiffener ring (Title and Abstract) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VALERIE N NEWTON/Examiner, Art Unit 2897 06/11/26 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/672,372 Page 2 Art Unit: 2897 Application/Control Number: 18/672,372 Page 3 Art Unit: 2897 Application/Control Number: 18/672,372 Page 4 Art Unit: 2897 Application/Control Number: 18/672,372 Page 5 Art Unit: 2897 Application/Control Number: 18/672,372 Page 6 Art Unit: 2897 Application/Control Number: 18/672,372 Page 7 Art Unit: 2897 Application/Control Number: 18/672,372 Page 8 Art Unit: 2897 Application/Control Number: 18/672,372 Page 9 Art Unit: 2897
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