Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Currently, claim 17 recites “wherein a middle one of the local back-side power rails is at a center point, in the height direction.” Currently, this raises some questions about definitiveness. For there to be a “middle one” of a thing in a direction, there needs to be at least three of said thing in said direction. Examiner wonders how the invention as claimed would still be able to have only two local back-side power rails or if the claim intends to limit there being at least three local back-side power rails. Currently there is a mismatch between the minimum number of elements and the descriptor of having a “middle,” as when there are only two elements there is no “middle one.” Examiner believes this fails to particularly point out and distinctively claim the subject matter of the invention. Appropriate action is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6-7, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable by United States Patent Application Publication by Peng et al. (US 20230411300 A1; Peng) in view of United States Patent Application Publication by Jain (US 20190259702 A1; Jain).
Regarding claim 1, Peng discloses a semiconductor device comprising:
a first stacked field-effect transistor (FET) (D1; Fig. 1A, where FET D1 is in a stack);
a second stacked FET (D2) adjacent the first stacked FET (Fig. 1A, where second stacked FET D2 is adjacent to first stacked FET D1);
a third stacked FET (D3) adjacent the second stacked FET (Fig. 1A, where third stacked FET D3 is adjacent to second stacked FET D2);
a fourth stacked FET (D4) adjacent the third stacked FET (Fig. 1A, where fourth stacked FET D4 is adjacent to third stacked FET D3); and
However, while Peng does disclose a back side power distribution structure (BSPD) and a power distribution structure (CPD) between and electrically connected to the first stacked FET and the second stacked FET, Peng fails to explicitly disclose that the CPD is a “first global back-side power rail.” The same can be said about the power distribution structure (CPD2) in Peng being disclosed and akin in location and for power delivery as the “second global back-side power rail” in the instant application, however similarly it is not explicitly disclosing that the (CPD2) is a “second global back-side power rail.” Additionally, Peng discloses a signal routing structure (SR2/SR3) between, and electrically connected to, the second stacked FET and the third stacked FET. However, the signal routing structure fails to explicitly be disclosed as a “local back-side power rail structure.”
In a similar field on endeavor, Jain discloses a similar device of stacked dies (Jain: 211, 212, 233, Fig. 2-2, Para. 42). Furthermore, Jain discloses both local and global power delivery between the stacked dies, wherein having first and second global power rail through the chimney stack (217/227/237 – Para. 45, 57, 61) and a local backside power rail (M5 - PDN metal layers, Para. 46-48). In view of the disclosure of Jain, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Jain to Peng at the time the instant application was filed to improve and incorporate local and global power delivery systems between the stacked FETS. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having power routing between die stacks can help to reduce IR drop without having to increase area and maintain the same cost per die (Jain: Para. 25).
Regarding claim 2, the combination of Peng and Jain discloses the semiconductor device of Claim 1, further comprising a contact (Peng: BSPD1 and/or BSPD2) that is in contact with both a transistor of the first stacked FET and a transistor of the second stacked FET,
wherein the first global back-side power rail is electrically connected to the transistor of the first stacked FET and the transistor of the second stacked FET via the contact (Peng: Para. 30, “Power distribution structure CPD1 is positioned between and electrically connects back side power distribution structure BSPD1 of die D1 to back side power distribution structure BSPD2 of die D2 by directly contacting each of back side power distribution structures BSPD1 and BSPD2.”)
The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP § 2114. The recitation of “wherein the second stacked FET is configured to transfer a voltage of the first global back-side power rail to the local back-side power rail” does not distinguish the present invention over the prior art of the combination of Peng and Jain who teaches the structure as claimed.
Regarding claim 3, the combination of Peng and Jain discloses the semiconductor device of Claim 2, and further wherein the contact is not in contact with the third stacked FET and is not in contact with the fourth stacked FET (Peng: Fig. 1A, where BSPD1 and BSPD2 are not in contact with the third D3 or fourth D4 stacked FET).
Regarding claim 4, the combination of Peng and Jain discloses the semiconductor device of Claim 2, further comprising a second contact (Peng: BSPD3 and/or BSPD4) that is in contact with both a transistor of the third stacked FET and a transistor of the fourth stacked FET,
wherein the second global back-side power rail is electrically connected to the transistor of the third stacked FET and the transistor of the fourth stacked FET via the second contact (Peng: Para. 30, “Power distribution structure CPD2 is positioned between and electrically connects back side power distribution structure BSPD3 of die D3 to back side power distribution structure BSPD4 of die D4 by directly contacting each of back side power distribution structures BSPD3 and BSPD4”).
Regarding claim 6, the combination of Peng and Jain discloses the semiconductor device of Claim 1, further comprising a contact (Peng: HB1) that is in contact with both a transistor of the second stacked FET and a transistor of the third stacked FET,
wherein the local back-side power rail is electrically connected to the transistor of the second stacked FET and the transistor of the third stacked FET via the contact (Peng: Para. 32, Where contact HB1 is in contact with the local power rails SR2/SR3 and contacts both transistors of the second and the third stacked FET).
Regarding claim 7, the combination of Peng and Jain discloses the semiconductor device of Claim 1, further comprising a second local back-side power rail (Peng: SR1 [as augmented by the combination of Jain]),
wherein the first stacked FET is adjacent, and electrically connected to, the second local back-side power rail (Fig. 1A. Para. 24).
Regarding claim 10, the combination of Peng and Jain discloses the semiconductor device of Claim 1, and further wherein the first stacked FET, the second stacked FET, the third stacked FET, and the fourth stacked FET are consecutive stacked FETs in a multi-height power-switch cell (Peng: Fig. 1A, where each of the stack FETS D1-D4 are stacked in a multi-height power-switch cell).
Regarding claim 11, the combination of Peng and Jain discloses the semiconductor device of Claim 10, and further wherein the multi-height power-switch cell comprises more than four stacked FETs (Peng: Para. 21, “In various embodiments, one or more of IC packages 100A-100C includes one or more dies in addition to the some or all of dies D1-D4 depicted in FIGS. 1A-1Cb, and/or one more of IC packages 100A-100C includes fewer than the some or all of dies D1-D4 depicted in FIGS. 1A-1Cb”).
Regarding claim 12, the combination of Peng and Jain discloses the semiconductor device of Claim 11, further comprising:
a fifth stacked FET (Peng, Para. 21, In alternate embodiments there would be more FET’s, of which there would be a fifth stacked FET (D5 - not labeled)), of the multi-height power-switch cell, adjacent the fourth stacked FET; and
a second local back-side power rail (SR4 - [as augmented by the combination of Jain]) between the fourth stacked FET and the fifth stacked FET (Where the embodiment of more FET’s not shown, there would a fifth stacked FET D5 above SR4 in Fig. 1A).
Regarding claim 14, the combination of Peng and Jain discloses the semiconductor device of Claim 1,
wherein the first global back-side power rail, the second global back-side power rail, and the local back-side power rail each extend longitudinally in a first direction, and are spaced apart from each other in a second direction that is perpendicular to the first direction (Peng: Fig. 1A, Where the CPD1, CPD2, SR2/SR3 all extend in the same x direction which we will call the first direction and are spaced apart in the z direction which we will call the second direction), and
wherein a width, in the second direction, of the first global back-side power rail is equal to a width, in the second direction, of the second global back-side power rail, and is equal to a width, in the second direction, of the local back-side power rail.
Peng shows the first global back-side power rail (Peng: CPD1), second global back-side power rail (Peng: CPD2), and the local back-side power rail (Peng: Either of SR2 or SR3) to be about the same height in the figures, however, Peng fails to explicitly disclose the height of each of said layers.
However, It would have been obvious to one of ordinary skill in the art at the time the invention was made to choose the same height of each local and global power rail, since it has been held by the courts that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding claim 15, the combination of Peng and Jain discloses the semiconductor device of Claim 14, further comprising:
a first contact (Peng: BSPD1) that is on the first global back-side power rail;
a second contact (Peng: BSPD4) that is on the second global back-side power rail; and
a third contact (Peng: HB1) that is on the local back-side power rail,
wherein the first contact and the second contact do not overlap the third contact in the first direction (Peng: Fig. 1A, Where the first direction is the labeled x direction and the contacts BSPD1, BSPD2, and HB1 don’t overlap in said direction).
Regarding claim 16, Peng discloses a semiconductor device comprising:
a multi-height switch cell (100A) comprising at least a quad cell height (Fig. 1A, where Cells D1-D4 all stacked making a quad cell height); and
Peng discloses power distribution structures (CPD) between first stacked FET and the second stacked FET, and additional power distribution structures (CPD2) between third stacked FET and the fourth stacked FET, as well as a signal routing structure (SR2/SR3) between second stacked FET and third stacked FET. However, Peng fails to explicitly disclose that the power distribution structures (CPD/CPD2) are global back-side power rails, and that signal routing structure (SR2/SR3) is a local power routing structure. While they are not explicitly stated to be local and global routing structures, the signal routing structure (SR2/SR3) and power distribution structures (CPD/CPD2) are still stacked alternatively along a height direction of the multi-height cell (Fig. 1A).
In a similar field on endeavor, Jain discloses a similar device of stacked dies (Jain: 211, 212, 233, Fig. 2-2, Para. 42). Furthermore, Jain discloses both local and global power delivery between the stacked dies and electrically connected to the multi-height switch cell, wherein having first and second global power rail through the chimney stack (217/227/237 – Para. 45, 57, 61) and a local backside power rail (M5 - PDN metal layers, Para. 46-48). In view of the disclosure of Jain, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Jain to Peng at the time the instant application was filed to improve and incorporate local and global power delivery systems alternating between the stacked Cells. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having power routing between die stacks can help to reduce IR drop without having to increase area and maintain the same cost per die (Jain: Para. 25).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable as obviousness by Peng in view of United States Patent by Fraser et al. (US 9780090 B2; Fraser).
Regarding claim 19, Peng discloses a semiconductor device comprising:
a multi-height switch cell (100A) comprising at least a quad cell height (Fig. 1A, where Cells D1-D4 all stacked making a quad cell height); and
a back-side power delivery network (BSPDN) (BSPD1-4) that is electrically connected to the multi-height power-gating cell (Para. 24).
However, Peng fails to disclose wherein the BSPDN comprises a first always-on back-side power rail and a second always-on back-side power rail that are each electrically connected to the multi-height power-gating cell.
In [0032], however, Fraser discloses a stacked transistors that can be powered with always on switch signal control nodes.
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select the first global back-side power rail and the second global back-side power rail to be always-on as in Fraser [0032], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose a always-on first and second global back-side power rails over other materials depending on manufacturing considerations such as cost of materials or time it takes to make the change.
Regarding claim 20, The combination of Peng and Fraser discloses the semiconductor device of Claim 19, and further wherein the BSPDN further comprises a normal back-side power rail that is between the first always-on back-side power rail and the second always-on back-side power rail (Peng: Where there are 4 backside power rails, someone of which are augmented by Fraser to be always-on, there will also be back-side power rails that are not always on can be between the always-on rails).
Claims 5, 18 are rejected under 35 U.S.C. 103 as being unpatentable as obviousness by Peng in view Jain and further in view of United States Patent Application Publication by Liebmann et al. (US 20220085012 A1; Liebmann).
Regarding claim 5, the combination of Peng and Jain discloses the semiconductor device of Claim 2, however, the combination of Peng and Jain fails to explicitly disclose that the transistors in the stacked FETS are PMOS or NMOS respectively.
In a similar field of endeavor, Liebmann discloses a similarly stacked FET device (1100) with 4 cells (Liebmann: Fig. 2/7, Para 36). Liebmann further discloses wherein the transistor of the first stacked FET (Liebmann: P1) and the transistor of the second stacked FET (Liebmann: P2) are respective p-type metal-oxide-semiconductor (PMOS) transistors (Liebmann: Para. 36),
wherein the PMOS transistor of the first stacked FET is on top of an n-type metal-oxide-semiconductor (NMOS) transistor (N1) of the first stacked FET (Liebmann: Fig. 10, if the device is turned upside down from the orientation of the figure, the PMOS transistor of the first stacked FET (P1) would be on top of an n-type metal-oxide-semiconductor (NMOS) transistor (N1)), and
wherein the PMOS transistor of the second stacked FET is on top of an NMOS transistor (N2) of the second stacked FET (Liebmann: Fig. 10, if the device is turned upside down from the orientation of the figure, the PMOS transistor of the second stacked FET (P2) would be on top of an n-type metal-oxide-semiconductor (NMOS) transistor (N2)).
In view of the disclosure of Liebmann, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Liebmann to the combination of Jain and Peng at the time the instant application was filed in order to disclose the FETS explicitly as n-type or p-type respectively. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that positioning p-type and n-type transistors in specific ways as so they share a gate, over/under in this and the instant applications case, can form a complementary FET device (Liebmann: Para. 10).
Regarding claim 18, the combination of Peng and Jain discloses the semiconductor device of Claim 16, and further wherein the multi-height switch cell comprises at least four stacked field-effect transistors (FETs) (Peng: D1-D4).
however, the combination of Peng and Jain fails to explicitly disclose wherein each of the stacked FETs comprises an n-type metal-oxide-semiconductor (NMOS) region and a p-type metal-oxide-semiconductor (PMOS) region that is on top of the NMOS region.
In a similar field of endeavor, Liebmann discloses a similarly stacked FET device (1100) with 4 cells (Liebmann: Fig. 2/7, Para 36). Liebmann further discloses wherein each of the stacked FETs comprises an n-type metal-oxide-semiconductor (NMOS) region and a p-type metal-oxide-semiconductor (PMOS) region that is on top of the NMOS region (Liebmann: Fig. 10, Fig. 1, if the device is turned upside down from the orientation of the figure, the PMOS transistor of the first stacked FET (P1) would be on top of an n-type metal-oxide-semiconductor (NMOS) transistor (N1) and the same for each of the stacked FET’s repeating)
In view of the disclosure of Liebmann, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Liebmann to the combination of Jain and Peng at the time the instant application was filed in order to disclose the FETS explicitly as n-type or p-type respectively. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that positioning p-type and n-type transistors in specific ways as so they share a gate, over/under in this and the instant applications case, can form a complementary FET device (Liebmann: Para. 10).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable as obviousness by Peng in view Jain and further in view of Fraser.
Regarding claim 8, the combination of Peng and Jain first global back-side power rail and the second global back-side power rail are respective always-on back-side power rails.
In [0032], however, Fraser discloses a stacked transistors that can be powered with always on switch signal control nodes.
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select the first global back-side power rail and the second global back-side power rail to be always-on as in Fraser [0032], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose a always-on first and second global back-side power rails over other materials depending on manufacturing considerations such as cost of materials or time it takes to make the change.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable as obviousness by Peng in view Jain and further in view of United States Patent Application Publication by Lin et al. (US 20210272852 A1; Lin).
Regarding claim 9, the combination of Peng and Jain discloses the semiconductor device of Claim 1, but fails to disclose gate-cuts between the stacked FETS.
With respect to the limitation of having “a first gate-cut between the first stacked FET and the second stacked FET; a second gate-cut between the second stacked FET and the third stacked FET; and a third gate-cut between the third stacked FET and the fourth stacked FET”, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have the gate-cuts between the stacked FETS since it was well known in the art that formation of gate-cut features in a stack structure can “enhance process window and improve device performance” (Lin: Para. 20). Using the stacked FET device with gate-cuts between each FET in the stack is a common practice in the art because enhance process window and improve device performance. Further, “[c]ommon sense teaches, however, that familiar items may have obvious uses beyond their primary purposes, and in many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” KSR Int’l Co. v. Teleflex Inc. 550 U.S.__, 82 USPQ2d 1385 (Supreme Court 2007).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 13, the prior art of record fails to disclose “wherein the multi-height power-switch cell is between the pair of non-power-switch standard cells, and wherein the local back-side power rail is electrically connected to each non-power-switch standard cell among the pair of non-power-switch standard cells.” Along with the other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 10am-6pm EST.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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