Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 08/25/2026 has been entered. Claims 1 – 15 are elected without traverse. Claims 16 – 19 are withdrawn. Claims 1 – 15 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 8 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bao (Pat. No. 10020254 B1), hereinafter Bao, in view of Iijima (Pub. No. 20210082944 A1), hereinafter Iijima.
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Regarding Independent Claim 1 (Original), Bao teaches a semiconductor device comprising:
a substrate ( Bao, FIG. 1, 16; col. 5, line 5, substrate 16 );
a first plug ( Bao, FIG. 1, via (V0); col. 5, line 23, metal conductor filled via (V0) ) disposed above the substrate ( Bao, FIG. 1, 16 ) and extending in a first direction ( Bao, FIG. 1, vertical direction ) that crosses an upper surface of the substrate ( Bao, FIG. 1, 16 );
a first interconnection ( Bao, FIG. 1, 20; col.5, line 19, metal conductor 20 (i.e., M1) ) disposed above and electrically connected to the first plug ( Bao, FIG. 1, via (V0) ), the first interconnection containing copper (col. 5, line 8, The metal conductor 12 can be copper; col. 5, line 22, As shown, … metal conductor filled via (V0) vertically extending from and electrically coupling the patterned metal (M1) 20 to the underlying patterned metal (M0) 12 );
a second interconnection ( Bao, FIG. 1, 12; col.5, line 3, metal conductor 12 ) disposed below and electrically connected to the first plug ( Bao, FIG. 1, via (V0) );
a second plug ( Bao, FIG. 1, 32; col. 5, line 36, super via 32 ) disposed above the substrate ( Bao, FIG. 1, 16 ) and extending in the first direction ( Bao, FIG. 1, vertical direction ), an upper end of the second plug ( Bao, FIG. 1, 32 ) being different in level from an upper end of the first plug ( Bao, FIG. 1, via (V0) ) and a lower end of the second plug ( Bao, FIG. 1, 32 ) being same in level as a lower end of the first plug ( Bao, FIG. 1, via (V0) ); and
a third interconnection ( Bao, FIG. 1, 12 below 32; col.5, line 3, metal conductor 12 ) disposed below and electrically connected to the second plug ( Bao, FIG. 1, 32 ).
Bao does not disclose:
a third plug disposed above and electrically connected to the second plug and extending in the first direction, the third plug containing tungsten;
However, Iijima teaches:
a third plug ( Iijima, FIG. 1A, 7, 7a, 7b ) disposed above and electrically connected to the second plug ( Iijima, FIG. 1A, 3 ) and extending in the first direction, the third plug ( Iijima, FIG. 1A, 7, 7a, 7b ) containing tungsten ( Iijima, FIG. 1A, 7, 7a, 7b above 3; [0027], wirings 3; [0031], The wirings 3 in the present embodiment are metal wirings containing copper (Cu), and are, for example, Cu wirings; [0033], FIG. 1A shows the insulating film 6 and the via plug 7 formed on the left wiring 3 … The first metal layer 7a in the present embodiment is a metal layer containing tungsten (W), and is, for example, a tungsten liner layer. In addition, the second metal layer 7b in the present embodiment is a metal layer containing tungsten (W), and is, for example, a tungsten plug material layer; [0003], it is desirable to prevent the reaction between the material of the wiring and the material of the via plug; [0053], According to the present embodiment, it is less likely to cause the reaction between the wiring 3 and the via plug 7 );
Bao and Iijima are both considered to be analogous to the claimed invention because they are forming interconnections ( or wirings ) and plugs ( or vias ) in semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bao ( FIG. 1, super via 32 ), to incorporate the teachings of Iijima ( FIG. 1A, 7, 7a, 7b above 3 ), to implement that “ a third plug ( Iijima, FIG. 1A, 7, 7a, 7b ) disposed above and electrically connected to the second plug ( Bao, FIG. 1, super via 32 ) and extending in the first direction, the third plug containing tungsten ( Iijima, FIG. 1A, 7, 7a, 7b; [0033], tungsten (W) ) ” ( Iijima, [0033], FIG. 1A shows the insulating film 6 and the via plug 7 formed on the left wiring 3 ). Doing so would prevent the reaction between the material of the wiring and the material of the via plug ( Iijima, [0003] ), and therefore avoid the problem that the Cu wiring reacts with the TiN film ( Iijima, [0051] ).
Regarding Claim 2 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Bao further teaches: further comprising:
a fourth plug ( Bao, FIG. 1, 30; col. 5, line 33, vias 30 (i.e., V1) ) disposed above and electrically connected to the first interconnection ( Bao, FIG. 1, 20 ), an upper end of the fourth plug ( Bao, FIG. 1, 30 ) being same in level as the upper end of the second plug ( Bao, FIG. 1, 32 ), wherein
the upper end of the second plug ( Bao, FIG. 1, 32 ) is above in level with respect to the upper end of the first plug ( Bao, FIG. 1, via (V0) ).
Regarding Claim 3 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Iijima further teaches: further comprising:
a stack of films ( Iijima, FIG. 15, FIG. 16, WL, 51; [0086], a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on the interlayer insulating film 13 (FIG. 15) ) including a plurality of electrode layers ( Iijima, FIG. 15, FIG. 16, WL ) stacked in the first direction and insulated ( Iijima, FIG. 15, FIG. 16, 51 ) from each other, the stack of films including:
a first area ( Iijima, FIG. 15, WL, 21, 22 ) located above the third plug ( Iijima, FIG. 1A, 7, 7a, 7b; FIG. 15, V, or plug between 22 and 23 ), the third plug ( Iijima, FIG. 15, plug between 22 and 23 ) being electrically connected to one of the electrode layers ( Iijima, FIG. 15, FIG. 16, WL ); and
a second area ( Iijima, FIG. 15, CL ) located above the fourth plug ( Iijima, FIG. 15, 42 or V );
a first columnar part ( Iijima, FIG. 15, CL; [0080], columnar portion CL; [0087], The columnar portion CL successively includes … a charge storage layer 53 … a channel semiconductor layer 55 ) extending through the stack of films ( Iijima, FIG. 15, FIG. 16, WL, 51 ) in the first direction in the second area ( Iijima, FIG. 15, CL ), the first columnar part including a first semiconductor layer ( Iijima, [0087], a channel semiconductor layer 55 ) extending in the first direction and a first charge accumulation layer ( Iijima, [0087], charge storage layer 53 ) disposed between the first semiconductor layer ( Iijima, [0087], a channel semiconductor layer 55 ) and the plurality of electrode layers ( Iijima, FIG. 15, FIG. 16, WL ); and
a fifth plug ( Iijima, FIG. 15, 24; [0080], via plug 24 ) disposed between the fourth plug ( Iijima, FIG. 15, 42 or V ) and the first columnar part ( Iijima, FIG. 15, CL ) and extending in the first direction ( Iijima, FIG. 15, vertical direction ).
Regarding Claim 4 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 3, on which this claim is dependent, Iijima further teaches:
wherein the first interconnection ( Iijima, FIG. 15, BL; [0080], bit line BL) serves as a bit line.
Regarding Claim 8 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 3, on which this claim is dependent, Iijima further teaches: wherein
the stack of films ( Iijima, FIG. 15, FIG. 16, WL ) further includes:
a third area ( Iijima, FIG. 15, CL in the adjacent memory cell array ) adjacent to the first area ( Iijima, FIG. 15, WL, 21, 22 ) in the second direction, with the first area ( Iijima, FIG. 15, WL, 21, 22 ) between the second area ( Iijima, FIG. 15, CL ) and the third area ( Iijima, FIG. 15, CL in the adjacent memory cell array ); and
a fourth area ( Iijima, FIG. 15, WL, 21, 22 in the adjacent memory cell array ) connecting the first area ( Iijima, FIG. 15, WL, 21, 22 ) and the third area ( Iijima, FIG. 15, CL in the adjacent memory cell array ) in the second direction, the fourth area being adjacent to the first area ( Iijima, FIG. 15, WL, 21, 22 ) in the third direction, and
the semiconductor device further comprises a second columnar part ( Iijima, FIG. 15, CL ) extending through the stack of films ( Iijima, FIG. 15, FIG. 16, WL ) in the first direction in the third area ( Iijima, FIG. 15, CL in the adjacent memory cell array ), the second columnar part ( Iijima, FIG. 15, CL ) including a second semiconductor layer ( Iijima, [0087], a channel semiconductor layer 55 ) extending in the first direction and a second charge accumulation layer ( Iijima, [0087], charge storage layer 53 ) disposed between the second semiconductor layer ( Iijima, [0087], a channel semiconductor layer 55 ) and the plurality of electrode layers ( Iijima, FIG. 15, FIG. 16, WL ).
Regarding Claim 9 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 8, on which this claim is dependent, Bao and Iijima further teach: further comprising:
a fifth interconnection ( Iijima, FIG. 1A, 3; FIG. 15, CL, 24, BL ) disposed below the third area ( Iijima, FIG. 15, CL in the adjacent memory cell array ) and electrically connected to the second columnar part ( Iijima, FIG. 15, CL ), the fifth interconnection ( Iijima, FIG. 1A, 3; FIG. 15, CL, 24, BL ) containing copper ( [0027], wirings 3; [0031], The wirings 3 in the present embodiment are metal wirings containing copper (Cu) ); and
an eighth plug ( Bao, FIG. 1, adjacent via (V0) ) disposed below and electrically connected to the fifth interconnection and extending in the first direction ( Bao, FIG. 1, vertical direction ), an upper end of the eighth plug ( Bao, FIG. 1, adjacent via (V0) ) being same in level as the upper end of the first plug ( Bao, FIG. 1, via (V0) ) and a lower end of the eighth plug being same in level as the lower end of the first plug ( Bao, FIG. 1, via (V0) ).
Regarding Claim 10 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Iijima further teaches: wherein
the second plug ( Iijima, FIG. 1A, 3 ) is disposed immediately below the third plug ( Iijima, FIG. 1A, 7, 7a, 7b ).
Regarding Claim 11 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Bao further teaches: wherein
the first plug ( Bao, FIG. 1, via (V0) ) and the second plug ( Bao, FIG. 1, 32; col. 5, line 36, super via 32; FIG. 10, 148 ) are formed of a same material ( Bao, col. 5, line 8, The metal conductor 12 can be copper; col. 9, line 29, a layer of copper is then deposited ).
Regarding Claim 12 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Bao further teaches: wherein
an outer diameter of the second plug ( Bao, FIG. 1, 32; col. 5, line 36, super via 32 ) at a level is larger than an outer diameter of the first plug ( Bao, FIG. 1, via (V0) ) at the level.
Regarding Claim 13 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Bao further teaches: wherein
the second interconnection ( Bao, FIG. 1, 12; col.5, line 3, metal conductor 12 ) and the third interconnection ( Bao, FIG. 1, 12 below 32; col.5, line 3, metal conductor 12 ) are formed of a same material ( Bao, col. 5, line 8, The metal conductor 12 can be copper ).
Regarding Claim 14 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Bao further teaches: further comprising:
an insulating layer ( Bao, FIG. 1, 18; col. 5, line 15, A dielectric nitride capping layer 18 such as silicon carbon nitride is provided on the first interconnect level ) disposed above and along the upper surface of the substrate and below the first interconnection ( Bao, FIG. 1, 20 ), the first plug ( Bao, FIG. 1, via (V0) ) and the second plug ( Bao, FIG. 1, 32 ) penetrating the insulating layer ( Bao, FIG. 1, 18 ).
Regarding Claim 15 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Iijima further teaches: further comprising:
a first transistor ( Iijima, FIG. 15, 31; [0081], a plurality of transistors 31 ) disposed on the substrate ( Iijima, FIG. 15, 15; [0081], substrate 15 ) and electrically connected to the second interconnection ( Iijima, FIG. 15, 33, 34, 35, 36; [0081], a plurality of contact plugs 33 provided on source diffusion layers or drain diffusion layers of the transistors 31, wiring layers 34 provided on the contact plugs 33 and including a plurality of wirings, and wiring layers 35 provided on the wiring layers 34 and including a plurality of wirings; [0082], wiring layers 36 ); and
a second transistor ( Iijima, FIG. 15, 31; [0081], a plurality of transistors 31 ) disposed on the substrate ( Iijima, FIG. 15, 15 ) and electrically connected to the third interconnection (Iijima, FIG. 15, 33, 34, 35, 36).
Claims 5 – 7 are rejected under 35 U.S.C. 103 as being unpatentable over Bao, in view of Iijima, further in view of Guo (Pub. No. 20220139950 A1), hereinafter Guo.
Regarding Claim 5 (Original), Bao and Iijima teach the semiconductor device as claimed in claim 3, on which this claim is dependent, Bao and Iijima further teach: further comprising:
a sixth plug ( Iijima, FIG. 15, V ) extending in the first direction below the first area ( Iijima, FIG. 15, WL ) of the stack films ( Iijima, FIG. 15, FIG. 16, WL, 51 ), the sixth plug being adjacent to the third plug ( Iijima, FIG. 1A, 7, 7a, 7b ) in the third direction and containing tungsten ( Iijima, [0033], FIG. 1A … The first metal layer 7a … a metal layer containing tungsten (W), … the second metal layer 7b … a metal layer containing tungsten (W), … ), an upper end of the sixth plug ( Iijima, FIG. 15, V ) being same in level as an upper end of the third plug ( Iijima, FIG. 1A, 7, 7a, 7b ) and a lower end of the sixth plug ( Iijima, FIG. 15, V ) being same in level as a lower end of the third plug ( Iijima, FIG. 1A, 7, 7a, 7b );
a seventh plug ( Iijima, FIG. 15, 42 ) disposed below and electrically connected to the sixth plug, an upper end of the seventh plug being same in level as the upper end of the second plug ( Bao, FIG. 1, 32 ) and a lower end of the seventh plug being same in level as the lower end of the second plug ( Bao, FIG. 1, 32 ); and
a fourth interconnection ( Iijima, FIG. 15, 41 ) disposed below and electrically connected to the seventh plug ( Iijima, FIG. 15, 42 ).
Bao and Iijima do not disclose:
a first segmentation part extending in a second direction that is along the upper surface of the substrate;
a second segmentation part extending in the second direction, the second segmentation part being adjacent to the first segmentation part in a third direction that is along the upper surface of the substrate, with the stack of films therebetween,
However, Guo teaches:
a first segmentation part ( Guo, FIG. 4, FIG. 5, 414, 514; [0088], a plurality of slit structures 414 each extending in WL direction can divide the 3D memory device into multiple memory fingers 442; [0112], slit structure 514 ) extending in a second direction that is along the upper surface of the substrate;
a second segmentation part ( Guo, FIG. 4, FIG. 5, 414, 514; [0088], a plurality of slit structures 414 each extending in WL direction can divide the 3D memory device into multiple memory fingers 442; [0112], slit structure 514 ) extending in the second direction, the second segmentation part being adjacent to the first segmentation part in a third direction that is along the upper surface of the substrate, with the stack of films ( Guo, FIG. 6, 623; [0102], conductive layers 623 can act as the control gates or word lines for the memory cells 340 ) therebetween,
Bao and Iijima are both considered to be analogous to the claimed invention because they are forming interconnections ( or wirings ) and plugs ( or vias ) in semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bao ( FIG. 1, Vo as first plug, 32 as second plug ) and Iijima ( FIG. 1A, 7, 7a, 7b as third plug ), to incorporate the teachings of Guo ( FIG. 4, FIG. 5, 414, 514 as segmentation parts ), to implement a first segmentation part and a second segmentation part. Doing so would have a plurality of slit structures, and therefore divide the 3D memory device into multiple memory fingers ( Guo, [0088] ).
Regarding Claim 6 (Original), Bao, Iijima and Guo teach the semiconductor device as claimed in claim 5, on which this claim is dependent, Bao further teaches: further comprising:
Wherein the seventh plug ( Bao, FIG. 10, V0, 148 ) includes a same material ( Bao, col. 9, line 27, Examples of seed layers are copper, copper manganese, and the like. Following deposition of the seed layer, a layer of copper is then deposited … the copper metal layer can include an alloying element such as C, N, O, Cl or S ) as the materials of the first plug ( Bao, FIG. 1, via (V0) ) and the second plug ( Bao, FIG. 1, 32 ).
Regarding Claim 7 (Original), Bao, Iijima and Guo teach the semiconductor device as claimed in claim 5, on which this claim is dependent, Bao further teaches:
wherein the second interconnection ( Bao, FIG. 1, 12 ), the third interconnection ( Bao, FIG. 1, 12 below 32 ), and the fourth interconnection are formed of a same material ( Bao, col. 5, line 8, The metal conductor 12 can be copper, aluminum, a combination thereof ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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