DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 29 - 49 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made with traverse in the reply filed on May 26, 2026. The Election/Restriction requirement still stands for the reasons as set forth in the Requirement for Restriction/Election dated March 26, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Taneda et al. (U.S. Patent Publication No. 2020/0092993).
Regarding claim 1, in Figure 9, Taneda discloses a printed circuit board, comprising: a first substrate (50) including a first wiring layer (52); a second substrate (12, Figure 9; 122, Figure 1) disposed on the first substrate and including a second wiring layer (14, Figure 1); a metal layer (56) disposed between the first and second substrates; and a bonding layer (55) disposed between the first and second substrates; wherein each of the first and second substrates includes an organic material (both layers 50 and 12 may include resin, paragraphs [0039] – [0040] and [0107]), and wherein the bonding layer includes an inorganic material (insulating layer 55 may include a filler made of silica, paragraph [0111]).
Regarding claim 2, Taneda discloses wherein the metal layer includes a first metal layer disposed on an uppermost side of the first substrate and a second metal layer disposed on a lowermost side of the second substrate (Figure 9).
Regarding claim 3, Taneda discloses wherein the first and second metal layers are bonded to each other such that side surfaces thereof are disposed to be shifted from each other (Figure 9).
Regarding claim 4, Taneda discloses wherein an upper surface of the first metal layer and a lower surface of the second metal layer are directly bonded to each other (Figure 9).
Regarding claim 5, Taneda discloses wherein a boundary surface between the upper surface of the first metal layer and the lower surface of the second metal layer has at least one protrusion protruding inwardly of the first and second metal layers. (Figure 9)
Regarding claim 6, Taneda discloses wherein the protrusion includes a diffusion wedge of metal particles (Figure 9).
Regarding claim 7, Taneda discloses wherein the metal layer further includes a third metal layer disposed between the first and second metal layers and including a metal different from that of the first and second metal layers (Figure 9).
Regarding claim 8, Taneda discloses wherein at least a portion of the third metal layer is disposed beyond at least one of an upper surface of the first metal layer and a lower surface of the second metal layer (Figure 9).
Regarding claim 9, Taneda discloses wherein each of the first and second metal layers includes copper (Cu), and wherein the third metal layer includes silver (Ag) or gold (Au) (Figure 9).
Regarding claim 10, Taneda discloses wherein the bonding layer includes an inorganic insulating film (paragraph [0111]).
Regarding claim 11, Taneda discloses wherein the inorganic insulating film includes SiO2, SiN or SiCN (paragraph [0111]).
Regarding claim 12, Taneda discloses wherein the first substrate includes a plurality of first insulating layers, a plurality of first wiring layers disposed on or in the plurality of first insulating layers, and a plurality of first via layers penetrating at least one of the plurality of first insulating layers, respectively, and wherein the second substrate includes a plurality of second insulating layer, a plurality of second wiring layers disposed on or in the plurality of second insulating layers, respectively, and a plurality of second via layers penetrating at least one of the plurality of second insulating layers, respectively, wherein at least one of the plurality of first insulating layers includes an organic material, and wherein at least one of the plurality of second insulating layers includes an organic material (Figure 9).
Regarding claim 13, Taneda discloses wherein density of at least one wiring of the plurality of second wiring layers is greater than density of at least one wiring of the plurality of first wiring layers (Figure 9).
Regarding claim 14, Taneda discloses wherein at least one of the plurality of second wiring layers includes a fine circuit pattern having a line/space of 2 μm/2 μm or less (paragraph [0046]); Figure 9).
Regarding claim 15, Taneda discloses wherein the second substrate has a thickness less than a thickness of the first substrate (Figure 9).
Regarding claim 16, Taneda discloses wherein an organic insulating material included in at least one of the plurality of second insulating layers is different from an organic insulating material included in at least one of the plurality of first insulating layers (Figure 9).
Regarding claim 17, Taneda discloses wherein, among the plurality of first via layers, a first via layer disposed on an uppermost side includes a first connection via connected to the metal layer, wherein among the plurality of second via layers, a second via layer disposed on a lowermost side includes a second connection via connected to the metal layer, and wherein the first and second connection vias are tapered in opposite directions (Figure 9).
Regarding claim 18, Taneda discloses wherein a width of an upper end of the first connection via is greater than a width of a lower end of the first connection via in a cross-section, and wherein a width of the lower end of the second connection via is greater than a width of an upper end of the second connection via in the cross-section (Figure 9).
Regarding claim 19, Taneda discloses wherein the first substrate includes a core-type multilayer printed circuit board, and wherein the second substrate includes a coreless-type multilayer printed circuit board (Figure 9).
Regarding claim 20, Taneda discloses a first resist layer disposed on a lower side of the first substrate; and a second resist layer disposed on an upper side of the second substrate, wherein the first resist layer has a plurality of first openings each exposing at least a portion of the first wiring layer disposed on a lowermost side of the plurality of first wiring layers, and wherein the second resist layer has a plurality of second openings each exposing at least a portion of the second wiring layer disposed on an uppermost side of the plurality of second wiring layers (Figure 9).
Regarding claim 21, Taneda discloses a plurality of first connection metals disposed on the plurality of first openings, respectively, and each connected to at least a portion of the first wiring layer disposed on the lowermost side; a plurality of second connection metals each disposed on at least a portion of the plurality of second openings and each connected to at least a portion of the second wiring layer disposed on the uppermost side; and a semiconductor chip disposed on the second resist layer and connected to a second wiring layer disposed on the uppermost side through the plurality of second connection metals (Figure 9).
Regarding claim 22, in Figure 9, Taneda discloses a printed circuit board, comprising: a first substrate (50) including a first wiring layer (52); a second substrate (12, Figure 9; 122, Figure 1) disposed on the first substrate and including a second wiring layer (14, Figure 1); a metal layer (56) disposed between the first and second substrates; and a bonding layer (55) disposed between the first and second substrates; wherein a wiring line having a minimum line width among wiring lines of the second wiring layer has a line width smaller than a line width of a wiring line having a minimum line width among wiring lines of the first wiring layer (Figure 9).
Regarding claim 23, Taneda discloses wherein a minimum distance among distances between wiring lines of the second wiring layer is smaller than a minimum distance among distances between wiring lines of the first wiring layer (Figure 9).
Regarding claim 24, Taneda discloses wherein a minimum pitch among pitches of wiring pads of the second wiring layer is smaller than a minimum pitch among pitches of wiring pads of the first wiring layer (Figure 9).
Regarding claim 25, Taneda discloses a heterogeneous metal layer disposed in the metal layer; wherein the heterogeneous metal layer includes a metal different from the metal layer (Figure 9).
Regarding claim 26, Taneda discloses wherein the bonding layer is disposed adjacent to the metal layer, and wherein a thickness of the bonding layer is substantially the same as a thickness of the metal layer (Figure 9).
Regarding claim 27, Taneda discloses wherein each of the first and second substrates includes an organic material, and wherein the bonding layer includes an inorganic material (paragraphs [0039] – [0040], [0107], and [0111]).
Regarding claim 28, Taneda discloses wherein the metal layer includes nano-twinned copper (Figure 9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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