Prosecution Insights
Last updated: October 04, 2026
Application No. 18/672,545

PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Final Rejection §102
Filed
May 23, 2024
Priority
Sep 13, 2023 — RE 10-2023-0121576
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
698 granted / 893 resolved
+10.2% vs TC avg
Strong +17% interview lift
Without
With
+17.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
43 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.4%
-6.6% vs TC avg
§102
47.0%
+7.0% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 893 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s arguments with respect to claims 1 – 19 have been considered, but they are not persuasive. Please see the ground(s) of rejection below. Thus, Applicant’s traversal of the instant rejection on these grounds is deemed unsuccessful. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 16 and 18 - 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (U.S. Patent No. 9,867,296). Regarding claim 1, in Figure 3, Kim discloses a printed circuit board comprising: a first insulating layer (108); a pad (106) disposed on an upper side of the first insulating layer; a protrusion (113) disposed on the pad; and a metal post (115) disposed on the pad and covering the protrusion, wherein the metal post has a tapered shape, such that a width of an upper surface of the metal post is smaller than a width of a lower surface of the metal post (Figure 3), and the metal post covers at least a portion of a side surface of the protrusion (bump 115 covers the inner side surface of layer 113). Regarding claim 2, Kim discloses wherein a width of the metal post is smaller than a width of the pad (Figure 3). Regarding claim 3, Kim discloses a solder resist layer disposed on the first insulating layer (Figure 3). Regarding claim 4, Kim discloses wherein the solder resist layer has an opening exposing at least a portion of the pad and at least a portion of the metal post (Figure 3). Regarding claim 5, Kim discloses a surface treatment layer covering at least a portion of an upper surface of the pad and at least a portion of the metal post (Figure 3). Regarding claim 6, Kim discloses wherein the pad comprises a first metal layer disposed on the first insulating layer, and a second metal layer disposed on the first metal layer (Figure 3). Regarding claim 7, Kim discloses wherein the protrusion includes a metal material (Figure 3). Regarding claim 8, Kim discloses a connection member disposed on the metal post (Figure 3). Regarding claim 9, Kim discloses a semiconductor chip disposed on the metal post and including a body and a connection pad, and the connection member connects the metal post and the semiconductor chip to each other (Figure 3). Regarding claim 10, Kim discloses wherein a width of a surface of the connection member facing the connection pad is greater than a width of a surface of the connection member facing the metal post (Figure 3). Regarding claim 11, in Figure 3, Kim discloses a method of manufacturing a printed circuit board, comprising: forming a pad (106) on a first insulating layer (108); forming a protrusion (113) on the pad; and forming a metal post (115) on the pad to cover the protrusion, wherein the metal post has a tapered shape, such that a width of an upper surface of the metal post is smaller than a width of a lower surface of the metal post (Figure 3), and the metal post covers at least a portion of a side surface of the protrusion (bump 115 covers the inner side surface of layer 113). Regarding claim 12, Kim discloses wherein the forming a metal post comprises forming a dry film on the first insulating layer, exposing and developing at least a portion of the dry film to expose at least a portion of the pad and at least a portion of the protrusion, and forming the metal post on the pad (Figure 3). Regarding claim 13, Kim discloses wherein the developing at least a portion of the dry film comprises injecting a developer containing a liquid material, to form an opening having a tapered shape, such that a width of an upper surface of the opening is smaller than a width of a lower surface of the opening (Figure 3). Regarding claim 14, Kim discloses wherein the forming a pad comprises forming a first metal layer on the first insulating layer by electroless plating, and forming a second metal layer on the first metal layer by electroplating, the forming a protrusion comprises forming the protrusion on the second metal layer by electroplating, and the forming a metal post comprises forming the metal post on the second metal layer by electroplating (Figure 3). Regarding claim 15, Kim discloses after the forming a metal post, forming a connection member on the metal post. (Figure 3) Regarding claim 16, Kim discloses before the forming a connection member, planarizing the metal post (Figure 3). Regarding claim 18, Kim discloses wherein the metal post has a tapered shape, such that a width of an upper surface of the metal post is smaller than a width of a lower surface of the metal post (Figure 3) Regarding claim 19, Kim discloses wherein a width of the metal post is smaller than a width of the pad (Figure 3). Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by You et al. (U.S. Patent Publication No. 2023/0189451). Regarding claim 17, in Figure 5, You discloses a printed circuit board comprising: a first insulating layer (200); a pad (110P) disposed on an upper side of the first insulating layer; a protrusion (protrusion disposed on upper surface of pad 110P, not labeled) disposed on and protruding upwardly from an upper surface of the pad, the protrusion having a width smaller than a width of the pad (Figure 5); and a metal post (500BP) disposed on the pad and covering an upper surface and a side surface of the protrusion (Figure 5), wherein the metal post contacts at least a portion of the upper surface of the pad (bump 500BP is filled in the hole H and covers the protrusion, thus, a small portion of the bottom surface of bump 500BP contacts pad 110P). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

May 23, 2024
Application Filed
Feb 25, 2026
Non-Final Rejection mailed — §102
May 26, 2026
Response Filed
Sep 16, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.2%)
2y 6m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 893 resolved cases by this examiner. Grant probability derived from career allowance rate.

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