DETAILED ACTION
1. Applicant’s election without traverse of Group III (Claims 28-33) in the reply filed on January 23, 2026 is acknowledged. Claims 1-27 have been canceled. New dependent claims 34-42 have been added. Thus claims 28-42 are pending and claim 28 is independent.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
3. This application filed on 05/23/2024 Claims Priority from Provisional Application 63468434 , filed 05/23/2023. Application No. 18672716 Claims Priority from Provisional Application
63468441, filed on 05/23/2023.
Information Disclosure Statement
4. The information disclosure statements (IDS) submitted on 11/14/2024 has been considered. The submission is in-compliance with the provisions of 37 CFR 1.97. Form PTO-1449 is signed and attached hereto.
Drawings
5. The drawings filed on May 23rd, 2024 are accepted.
Specification
6. The specification filed on May 23rd, 2024 is also accepted.
Claim Objections
a. Independent claim 28, is objected to because of the following informalities: Claim 28, recites the limitation, “the dark rate count” at lines 5-6 of claim 28. It is not clear whether it is referring to the “a dark count rate” recited at line 3 of claim 28.
For the purpose of examination both are interpreted as “dark count rate”
Appropriate correction is required.
b. Dependent claims 29-42 depend on independent claim 28 and carry the deficiencies of the above independent claim 28 and are likewise objected.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. Claims 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan Cao et al (herein after referred as Cao, NPL document, titled, “CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication”, IEEE, November 2015) in view of Md. Sakibur Sajal et al (herein after referred as Sajal, NPL document titled, “Perimeter-Gated Single-Photon Avalanche Diode Imager with Vanishing Room Temperature Dark Count Probability”, IEEE, 2022)
The following is referring to independent claim 28
As per independent claim 28, Cao discloses an imager chip [Abstract, and page 26354, “CMOS image sensor chip”, “Page 2630, Abstract, “This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that in volves image sensor as a trusted entity”. Page 2630, right column, 3rd , “In this paper, we proposed a new CMOS image sensor based PUF for on-chip authentication and identification” A CMOS image sensor which is an integrated imager chip corresponds to the limitation, “an imager chip “ Note: A Complementary Metal-Oxide Semiconductor (CMOS) image sensor is a type of image sensor technology inside some digital cameras. It consists of an integrated circuit that records an image. A monolithic CMOS imager is an integrated imager chip] comprising:
an array of pixels, the array including a set of pixels [Page 2630, Section 3, right column A. “CMOS Image Sensor Fundamentals”, A typical architecture of a CMOS image sensor consists of a pixel array, vertical and horizontal scanners, and readout circuits and page 2633, section IV, right column, The image sensor ASIC mainly consistsofa64x 643T-APS array “.],
one or more physically unclonable functions [This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that in volves image sensor as a trusted entity”. Page 2630, right column, 3rd paragraph, “In this paper, we proposed a new CMOS image sensor based PUF for on-chip authentication and identification” and Page 2631, Right Column, B., 1st sentence, “The response of the proposed PUF is a binary string extracted from the pixel array ]“, the one or more physically-unclonable functions being dependent on the dark count rate of the variation of the output pixel /the dark signal non-uniformity (DSNU) of fixed pattern noise (FPN) [Page 2629, right column, 3rd paragraph, “In this paper, we proposed a new CMOS image sensor based PUF for on-chip authentication and identification. It exploits the dark signal non-uniformity (DSNU) of fixed pattern noise (FPN) in a CMOS image sensor to generate a unique and re liable signature. FPN as a whole refers to the variations in the output pixel voltage values, under uniform illumination, due to the device and interconnect mismatches across an image sensor” and Page 2631, Right Column, B., 1st sentence, “The response of the proposed PUF is a binary string extracted from the pixel array. Examiner Note. The dark signal non-uniformity (DSNU) of fixed pattern noise (FPN) broadly corresponds to the claim limitation the “dark rate count of the variation of the output pixel” Examiner Note: See the secondary prior art Sajal which supports this interpretation].
Cao discloses “the one or more physically-unclonable functions being dependent on the DSNU dark signal non-uniformity (DSNU) of fixed pattern noise (FPN) OR the dark rate count of the variation of the output pixel” but
Cao doesn’t explicitly disclose the following underlined claim limitation:
“each pixel in the set having a dark count rate;”
However, Sajal, discloses “each pixel in the set having a dark count rate” [Figure 5, Pixel array dark count rate color maps (in Hz). This figure visually shows that each pixel has a dark count rate. The rates vary spatially across the array. Furthermore, page 2, figure 3, “Fig. 3: Local dark count rate measurements for 16 adjacent pixels” this statement shows that dark count rate is measured individually for multiple pixels, which implies that each pixel possesses its own dark count rate.]
Examiner Note: Furthermore, Sajal on Page 2, 1st left column after figure 2 discloses the following supporting examiner’s interpretation that the DSNU as spatial variation in the array’ dark count. “We define the DSNU as the spatial variation in the array’s dark count rate” Furthermore Sajal on page 3, left column Section B, 2nd paragraph teaches the following supporting again examiner’s interpretation, “Fig.5(a)), the data showed that the array had a fixed-pattern noise (FPN) profile, and the dark signal non-uniformity (DSNU) that arises from the pixels inherently having different nominal dark count rates” Furthermore, as it is shown above, Sajal is quoted as defining DSNU as the spatial variation in the array’s dark count rate, and further explains that DNSU/FPN arises because pixels inherently have different nominal dark count rates. Because of this the premise Sajal expressly ties DSNU and dark count rate together.
Cao relied on for the PUF architecture and for teaching that the PUF response depends on pixel-output variation/dark non-uniformity, while Sajal is relied on for the express teachings that the relevant pixel-level dark behavior is characterized in terms of per-pixel dark count rate.
Both references are in the same sensor field and deal with pixel-level dark behavior in image-sensor arrays. Once Sajal teaches characterizing that behavior as per-pixel dark count rate, using that known characterization in Cao’s PUF framework would have been a straightforward and predictable variation-either as a known substitution, a known technique applied to a similar device or a predictable way to qualify the same underlying phenomenon for signature generation.
Cao and Sajal are an analogous in the same field of endeavor as they both are directed to CMOS image sensor technology comprising pixel arrays and associated pixel-level characteristics.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the PUF architecture of Cao using the mechanism such as “each pixel in the set having a dark count rate” as per teaching of Sajal for enhancing the security by generating device unique signatures and for deriving PUF responses from random dark count behavior of pixel, thereby improving the robustness of hardware-based key generation and authentication mechanisms. [See Sajal, Dark count rate measurement for adjacent pixels…]
The following is referring to dependent claims 29-31:
As per dependent claim 29, Cao discloses an imager chip [Abstract, and page 26354, “CMOS image sensor chip”, “Page 2630, Abstract, “This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that in volves image sensor as a trusted entity”. Page 2630, right column, 3rd , “In this paper, we proposed a new CMOS image sensor based PUF for on-chip authentication and identification” A CMOS image sensor which is an integrated imager chip corresponds to the limitation, “an imager chip “ Note: A Complementary Metal-Oxide Semiconductor (CMOS) image sensor is a type of image sensor technology inside some digital cameras. It consists of an integrated circuit that records an image. A monolithic CMOS imager is an integrated imager chip]
Cao doesn’t explicitly disclose the following underlined claim limitation:
“each pixel includes a perimeter-gated photodiode, the perimeter-gated photodiode including a gate terminal”
However, Sajal, discloses “each pixel includes a perimeter-gated photodiode [Abstract—"We report on a perimeter-gated single-photon avalanche diode (pg-SPAD) imager fabricated in a 0.35 µm CMOS process, The imager had 4,096 pixels disposed in a two dimensional array (64 × 64)” and page 2, left column , II, “The imager includes 4,096 pg-SPADs arranged in a 64 × 64 array” This teaches pixels implemented as perimeter-gated photodiode ], the perimeter-gated photodiode including a gate terminal [Page 2, left column, II, 2nd paragraph, “The pg-SPAD is formed with an n-well cathode (labeled VC), an anode made with a p+ implant in the n-well (labeled VA), and a poly-silicon perimeter gate disposed around the p+ implant” Page 2, right column, 5th paragraph, “perimeter gate voltage magnitude range of 0 to 8 V” Note: The perimeter gate that receives applied voltage constitutes the gate terminal of the perimeter gated photodiode.]
Cao and Sajal are an analogous in the same field of endeavor as they both are directed to CMOS image sensor technology comprising pixel arrays and associated pixel-level characteristics.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the PUF architecture of Cao using the mechanism such as “each pixel includes a perimeter-gated photodiode, the perimeter-gated photodiode including a gate terminal” as per teaching of Sajal in order to employ a known pixel structure in an image sensor system and furthermore for enhancing the security by generating device unique signatures and for deriving PUF responses from random dark count behavior of pixel, thereby improving the robustness of hardware-based key generation and authentication mechanisms. [See Sajal, Dark count rate measurement for adjacent pixels…]
As per dependent claim 30, Cao discloses one or more physically unclonable functions [This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that in volves image sensor as a trusted entity”. Page 2630, right column, 3rd paragraph, “In this paper, we proposed a new CMOS image sensor based PUF for on-chip authentication and identification” and Page 2631, Right Column, B., 1st sentence, “The response of the proposed PUF is a binary string extracted from the pixel array ]
Cao doesn’t explicitly disclose the following underlined claim limitation:
alterable by altering a voltage applied to the gate terminal.
However, Sajal, discloses, “altering a voltage applied to the gate terminal” [” Page 2, right column, 5th paragraph, “perimeter gate voltage magnitude range of 0 to 8 V” and page 3, figure 5, “Fig.5: (a)-(d)Pixel array dark count rate color maps (in Hz) as a function of perimeter gate (PG) voltage]. (Note: This teaches that changing the perimeter gate voltage alters the behavior of the pixel, including the dark count rate of the SPAD pixel, As shown on claim 28, above PUF depends on the pixel dark count rate, altering the gate voltage-which alters the dark count rate correspondingly alters the PUF response).
Cao and Sajal are an analogous in the same field of endeavor as they both are directed to CMOS image sensor technology comprising pixel arrays and associated pixel-level characteristics.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the PUF architecture of Cao using the mechanism such as “altering a voltage applied to the gate terminal” as per teaching of Sajal in order to alter the PUF response by adjusting the gate voltage and furthermore for enhancing the security by generating device unique signatures and for deriving PUF responses from random dark count behavior of pixel, thereby improving the robustness of hardware-based key generation and authentication mechanisms. [See Sajal, Dark count rate measurement for adjacent pixels…]
As per dependent claim 31, the combination of Cao and Sajal discloses an imager chip as applied to claim 29 above. Furthermore, Sajal discloses the imager chip wherein the perimeter-gated photodiode is a perimeter-gated single-photon avalanche diode (pg-SPAD) [[Abstract—"We report on a perimeter-gated single-photon avalanche diode (pg-SPAD) imager fabricated in a 0.35 µm CMOS process, The imager had 4,096 pixels disposed in a two dimensional array (64 × 64)” and page 2, left column , II, “The imager includes 4,096 pg-SPADs arranged in a 64 × 64 array”…”The pg-SPAD is formed with an n-well cathode (labeled VC), …and a poly-silicon perimeter gate disposed around the p+ implant” These statements discloses pixel implemented as a perimeter gated single-photon avalanche diodes (pg-SPAD)]
9. Claim 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan Cao et al (herein after referred as Cao, NPL document, titled, “CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication”, IEEE, November 2015) in view of Md. Sakibur Sajal et al (herein after referred as Sajal, NPL document titled, “Perimeter-Gated Single-Photon Avalanche Diode Imager with Vanishing Room Temperature Dark Count Probability”, IEEE, 2022) and further in view of CHEN, JIEZHI et al (herein after referred as Chen) (WO2018/196266 A1, Pub Date: 01/11/2018)
As per dependent claim 33, the combination of Cao and Sajal discloses an imager chip as applied to claim 29 above. Furthermore, Cao discloses an imager chip [Abstract, and page 26354, “CMOS image sensor chip”, “Page 2630, Abstract, “This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that in volves image sensor as a trusted entity”. Page 2630, right column, 3rd paragraph, “In this paper, we proposed a new CMOS image sensor based PUF for on-chip authentication and identification” A CMOS image sensor which is an integrated imager chip corresponds to the limitation, “an imager chip “ Note: A Complementary Metal-Oxide Semiconductor (CMOS) image sensor is a type of image sensor technology inside some digital cameras. It consists of an integrated circuit that records an image. A monolithic CMOS imager is an integrated imager chip]
The combination of Cao and Sajal doesn’t explicitly disclose the following underlined claim limitation: “wherein the one or more physically- unclonable functions comprise one or more fingerprints stored on the imager chip”
However, Chen discloses “wherein the one or more physically- unclonable functions comprises one or more fingerprints stored on the imager chip” [Abstract, “A physical unclonable function (PUF)-based camera image storage system, comprising an image sensor, an A/D converter, a digital signal processor and a memory which are sequentially connected. The memory comprises a processing module, a PUF fingerprint module and a storage module; a light signal enters a camera, is optically processed by the image sensor, and then enters the A/D converter; an analog signal is converted into a digital signal, and image pixel information is stored into the memory after being processed by the digital signal processor; and the processing module receives the information that is processed by the digital signal processor, processes the same, and selects the pixel information bits to carry out logical operations and receives a value generated by the PUF fingerprint module for carrying out the logical operations”]
Cao, Sajal and Chen are all an analogous in the same field of endeavor as they all are directed to image sensor technology comprising pixel arrays and associated pixel-level characteristics.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the PUF architecture of Cao and Sajal using the mechanism such as “the one or more physically- unclonable functions comprises one or more fingerprints stored on the imager chip” as per teaching of Chen in order to enhance the security by creating a physical information of memory chips which may be neither be replicated nor cracked. [See Chen, Abstract, Physical information of memory chips which may not be replicated, and the encrypted data may neither be replicated nor cracked. Therefore, the goal of high-reliability data encryption may be achieved, the embedded watermark information is more covert,….]
As per dependent claim 34, the combination of Cao, Sajal and Chen discloses an imager chip as applied to claim 33 above. Furthermore, Sajal discloses the imager chip wherein: the dark rate count for each pixel [[Figure 5, Pixel array dark count rate color maps (in Hz). This figure visually shows that each pixel has a dark count rate b. The rates vary spatially across the array. Furthermore, See page 2, figure 3, “Fig. 3: Local dark count rate measurements for 16 adjacent pixels” this statement shows that dark count rate is measured individually for multiple pixels, which implies that each pixel possesses its own dark count rate.]is a number of dark counts that occurred at that pixel during a predetermined integration time [Page 2, right column, 1st paragraph, “each pixel was activated for a fixed integration time (Tint)’…”The count rate (expressed herein in Hertz) was calculated by dividing the mean count by the integration time]; and the dark count is a number of events[Page 2, right column , 1st paragraph, ”The count rate (expressed herein in Hertz) was calculated by dividing the mean count by the integration time” This teaches that the “count” corresponds to events detected by SPAD pixel, which are counted to determine the dark count rate] that occur resulting from a noise process not related to photon generation [Abstract, “We further demonstrate that the array-wide noise variance decreases with an increase in perimeter gate voltage magnitude and page 1, right column, paragraph 2, “effects of perimeter gating on array-wide dark count rates as a function of pixel integration time in order to determine the operational characteristics that yield the best noise performance” and page 2, right column, 3rd paragraph, “However, because dark count generation is a statistical process” This teaches that dark counts arise from a statistical process rather than photon detection].
Allowable Subject Matter
10. Dependent claims 32 and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. The following is an examiner’s statements of reasons for allowance:
Regarding dependent claim 32, the above prior arts of record including the rest of the cited prior arts either taken alone or in combination neither anticipates nor renders obvious the claimed subject matter of the instant application that is taken as a whole including the following specific limitation, “The imager chip …wherein the one more physically unclonable functions is concealable using the gate terminal”.
For this reason, the specific claim limitations recited in dependent claim 32 taken as whole are found to be allowable.
Regarding dependent claim 35, the above prior arts of record including the rest of the cited prior arts either taken alone or in combination neither anticipates nor renders obvious the claimed subject matter of the instant application that is taken as a whole including the following specific limitation, “The imager chip…wherein: the one or more fingerprints are created from a normalized dark count map comprising the dark rate count for each pixel in the array when the array is exposed to darkness; and the one or more fingerprints are combined to generate a set of keys”.
For this reason, the specific claim limitations recited in dependent claim 35 taken as whole are found to be allowable.
12. The dependent claims 36-42 which are dependent on the above dependent claim 35 being further limiting to the dependent claims, definite and enabled by the specification would also be allowed if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A. US Publication No. 20190123916A1 to Facon discloses Synthetic Physically Unclonable Function derived from an imaging sensor.
B. US Publication No. US20250280208A1 Maekelae discloses a system for modifying a dark current image is configurable to receive an input image depicting a dark current state for one or more pixels of the input image, The dark current state for one or more pixels of the input image comprises one of: a faulty state or a non-faulty state. The system is configurable to partition the input image into a plurality of partitions and generate an updated input image by imposing at least one quantity constraint or at least one severity constraint to the plurality of partitions in association with at least one type of dark current state.
C. US Publication No. 20190121955A1 Facon discloses key generation from an imaging sensor
D. See the other cited prior arts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMSON B LEMMA whose telephone number is 571-272-3806. The examiner can normally be reached on M-F 8am-10pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shaw Yin Chen can be reached on to 571-272-8878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMSON B LEMMA/Primary Examiner, Art Unit 2498
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