DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/23/2024, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7, 10-11, and 14-23 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oh et al. (US 20230132272) herein referred to as Oh (US 20230132272).
As to claim 1, (Original): Oh discloses a semiconductor package comprising:
a first semiconductor chip (1st chip 100) comprising a substrate interconnects (Annotated IC structure, Oh) first surface of the substrate, an insulating layer (insulating layer 120) on at least a portion of the interconnects (Annotated IC structure), first lower pads (1st lower pads 150) on the interconnects, and a first passivation layer (material of IC structure 125) on at least a portion of each of the first lower pads (lower pads 150); and
a second semiconductor chip (2nd chip 500) comprising second upper pads (Fig. 8 2nd upper pads 160) in contact with the first lower pads (Fig. 8, 1st lower pads 150), a second passivation layer (first base insulating layer 130) on at least a portion of each of the second upper pads (Fig. 8, 2nd upper pads 160) and in contact with the first passivation layer (material of IC structure 125), second lower pads (Fig. 8, 2nd lower pads 155) opposite to the second upper pads (Fig. 8, 2nd upper pads 160), and through-electrodes (Fig. 8 penetration vias 115) electrically connecting the second upper pads (Fig. 8, 2nd upper pads 165) and the second lower pads (Fig. 8, 2nd lower pads 155), wherein
in a plan view, the first semiconductor chip (Fig. 1, 1st chip 100) has a first longer side (Fig. 1, 1st longer side of chip 100) extending in a first direction (x direction of Oh Fig. 1) and a first shorter side (Fig. 1, 1st shorter side of chip 100) extending in a second direction (y direction of Oh Fig. 1), intersecting the first direction, wherein
the interconnects comprise intermediate conductors (Annotated intermediate conductors Fig. 7, Oh) and connection conductors (Annotated connection conductors Fig. 7, Oh) between the intermediate conductors and the first lower pads (Fig. 7, 1st lower pads 150),
a thickness of each of the connection conductors (Annotated connection conductors Fig. 7, Oh) being greater than a thickness of each of the intermediate conductors (Annotated intermediate conductors Fig. 7, Oh), and wherein
the connection conductors (Annotated connection conductors Fig. 7, Oh) are disposed in the first direction and the second direction, and a number of the connection conductors in the first direction is greater than a number of the connection conductors in the second direction. (Plan view Fig. 1 discloses a rectangular device which implicitly has more connection conductors along the longer side direction than the number of connection conductors in the shorter side direction. Device is a rectangle not a square device.)
PNG
media_image1.png
697
1551
media_image1.png
Greyscale
As to claim 2, (Original): Oh discloses the semiconductor package of claim 1 as discussed above, and further discloses, wherein
each of the connection conductors have first sides extending in the first direction and second sides extending in the second direction (Annotated connection conductors Fig. 7, Oh), and wherein
a length of each of the first sides is shorter than a length of each of the second sides (Annotated connection conductors Fig. 7, Oh).
As to claim 3, (Original): Oh discloses the semiconductor package of claim 2 as discussed above, and further discloses, wherein
a first ratio of a sum of lengths of the first sides adjacent to the first longer side and a length of the first longer side is lower than a second ratio of a sum of lengths of the
PNG
media_image2.png
548
860
media_image2.png
Greyscale
second sides adjacent to the first shorter side and a length of the first shorter side. (Plan view Fig. 1 discloses a rectangular device which implicitly meets the limitations of claim 3. Device is a rectangle not a square device.)
As to claim 5, (Original): Oh discloses the semiconductor package of claim 1 as discussed above, and further discloses, wherein
a number of first spaces between the connection conductors in the first direction is greater than a number of second spaces between the connection conductors in the second direction. (Plan view: Fig. 1 discloses a rectangular device which implicitly has more first spaces between connection conductors along the longer side first direction than the number of second spaces connection conductors in the shorter side second direction. Device is a rectangle not a square device.)
As to claim 7, (Original): Oh discloses the semiconductor package of claim 5 as discussed above, and further discloses, wherein
the first spaces do not overlap the connection conductors in the second direction (See Annotated Fig. 1, 1st space, Oh) .
As to claim 10, (Original): Oh discloses the semiconductor package of claim 1 as discussed above, and further discloses, wherein
the connection conductors comprise a second group of connection conductors connected 1:1 to the first lower pads (Annotated Oh Fig. 1, 2nd group).
As to claim 11, (Original): Oh discloses the semiconductor package of claim 1 as discussed above, and further discloses, wherein
the connection conductors comprise a third group of connection conductors spaced apart from the first lower pads (Annotated Oh Fig. 1, 3rd group).
As to claim 14, (Original): Oh discloses the semiconductor package of claim 1 as discussed above, and further discloses, wherein
the first semiconductor chip (Fig. 7, 1st chip 100) comprises a plurality of first semiconductor chips stacked in a vertical direction on the second semiconductor chip (2nd chip 500), and wherein
at least some of the plurality of first semiconductor chips are on the second surface of the substrate (Fig. 7), and comprise
first upper pads (Annotated Oh Fig. 8, (161)) in contact with the first lower pads (Fig. 8, 1st lower pads 150), adjacent to each other in the vertical direction (Fig. 7),
an upper passivation layer (layer 140) on at least a portion of each of the first upper pads (Annotated Oh Fig. 8, (161)) and in contact with the first passivation layer (material of IC structure 125) adjacent thereto in the vertical direction, and
through-electrodes (Fig. 8 penetration vias 115) penetrating through the substrate and electrically connecting the first upper pads (Annotated Oh Fig. 8, (161)) to the first lower pads (Fig. 8, 1st lower pads 150).
PNG
media_image3.png
361
505
media_image3.png
Greyscale
As to claim 15, (Original): Oh discloses a semiconductor package comprising:
a first semiconductor chip (1st chip 100) comprising interconnects, first lower pads (1st lower pads 150) on the interconnects, and a first passivation layer (material of IC structure 125) on at least a portion of each of the first lower pads (1st lower pads 150); and
a second semiconductor chip (2nd chip 500) comprising second upper pads (Fig. 8, 2nd upper pads 160), in contact with the first lower pads (1st lower pads 150),
a second passivation layer (first base insulating layer 130) on at least a portion of each of the second upper pads (Fig. 8, 2nd upper pads 160) and in contact with the first passivation layer (material of IC structure 125), second lower pads (Fig. 8, 2nd lower pads 155) opposite to the second upper pads (Fig. 8, 2nd upper pads 160), and
through-electrodes (Fig. 8 penetration vias 115) electrically connecting the second upper pads (Fig. 8, 2nd upper pads 160), and the second lower pads (Fig. 8, 2nd lower pads 155), wherein
the interconnects (Annotated IC structure, Oh) comprise intermediate conductors (Annotated intermediate conductors Fig. 7, Oh) and top conductors (Fig. 1, [0032]”The substrate 110 may be formed of or may include at least one of semiconductor materials (e.g., silicon, germanium, or silicon germanium”). between the intermediate conductors and the first lower pads (1st lower pads 150), wherein,
in a plan view, the first semiconductor chip (Fig. 1, 1st chip 100) has a first longer side (Fig. 1, 1st longer side of chip 100) extending in a first direction and a first shorter side (Fig. 1, 1st shorter side of chip 100) extending in a second direction, intersecting the first direction, and wherein,
in the plan view, the top conductors has first sides having a first length in the first direction, and second sides having a second length longer than the first length in the second direction (Annotated top conductors Oh, Fig. 1).
As to claim 16, (Original): Oh discloses the semiconductor package of claim 15 as discussed above, and further discloses, wherein
the first lengths of the first sides are equal to each other (See Fig. 7).
As to claim 17, (Original): Oh discloses the semiconductor package of claim 15 as discussed above, and further discloses, wherein
the top conductors comprise a first group of top conductors and a second group of top conductors, (Annotated conductors Oh, Fig. 1) and wherein
lengths of the second sides of the first group of top conductors are different from lengths of the second sides of the second group of top conductors (Annotated conductors Oh, Fig. 1).
As to claim 18, (Original): Oh discloses the semiconductor package of claim 17 as discussed above, and further discloses, wherein
the lengths of the second sides of the first group of the top conductors is greater than the lengths of the second sides of the second group of the top conductors (Annotated conductors Oh, Fig. 1).
As to claim 19, (Original): Oh discloses the semiconductor package of claim 18 as discussed above, and further discloses, wherein
the intermediate conductors comprise a signal interconnection, a power interconnection, and a ground interconnection, wherein
the first group of the top conductors (Annotated top conductors Oh, Fig. 1) are connected to at least one of the power interconnection and the ground interconnection (implicitly in order to have a functioning device), and wherein
the second group of the top conductors (Annotated second group of top conductors Oh, Fig. 1) are connected to the signal interconnection (implicitly in order to have a functioning device),.
As to claim 20, (Original): Oh discloses a semiconductor package comprising:
a first semiconductor chip (1st chip 100) comprising interconnects, first lower pads (1st lower pads 150) on the interconnects, and a first passivation layer (material of IC structure 125) on at least a portion of each of the first lower pads (1st lower pads 150);
a second semiconductor chip (2nd chip 500) comprising second upper pads (Fig. 8, 2nd upper pads 160), in contact with the first lower pads (Fig. 8, 1st lower pads 150), and a second passivation layer (first base insulating layer 130) on at least a portion of each of the second upper pads (Fig. 8, 2nd upper pads 160) and in contact with the first passivation layer (material of IC structure 125); and
a mold layer on the second semiconductor chip (2nd chip 500) and adjacent to at least a side surface of the first semiconductor chip (As disclosed in Fig. 14, [0088] “In an embodiment, the mold layer 800 may be provided to cover the top surface of the uppermost one of the first semiconductor chips 100. However, the inventive concept is not limited to this example, and in an embodiment, the mold layer 800 may be provided to expose the top surface of the uppermost one of the first semiconductor chips 100, unlike the illustrated structure. “), wherein,
in a plan view, the first semiconductor chip (Fig. 1, 1st chip 100) has a first longer side (Fig. 1, 1st longer side of chip 100) extending in a first direction and a first shorter side (Fig. 1, 1st shorter side of chip 100) extending in a second direction, intersecting the first direction, wherein,
in the plan view, the second semiconductor chip ([0084] Fig. 13, 2nd chip 500 is mounted on the package substrate 700) has a second longer side that is longer than the first longer side in the first direction, and
a second shorter side that is longer than the first shorter side in the second direction ([0084] Fig. 13, 2nd chip 500 is mounted on the package substrate 700), wherein
the interconnects comprise intermediate conductors (Annotated intermediate conductors Fig. 7, Oh) and top conductors (Annotated top conductors Oh, Fig. 1) connecting the intermediate conductors and the first lower pads (Fig. 7, 1st lower pads 150), and wherein
each of the top conductors has a rectangular shape elongated in the second direction (Annotated top conductors Oh, Fig. 1).
As to claim 21, (Original): Oh discloses the semiconductor package of claim 20 as discussed above, and further discloses, wherein, in the plan view,
the first semiconductor chip (1st chip 100) comprises a first circuit region extending in the first direction, and a second circuit region adjacent to at least one side of the first circuit region in the second direction, and wherein (Circuit regions implicitly extend in the first and second direction of semiconducting devices, serving the primary purpose of manipulating and controlling the flow of electrical current to enable switching, amplification, and logic processing so as to use an industrially tested and accepted device.)
the top conductors comprise a first group of top conductors in the first circuit region and a second group of top conductors in the second circuit region (conductors in two regions must be connected to circuits of those regions implicitly in order to have a functioning device),.
As to claim 22, (Original): Oh discloses the semiconductor package of claim 21 as discussed above, and further discloses, wherein
a length of each of the first group of the top conductors in the second direction is greater than a length of each of the second group of the top conductors in the second direction. (Annotated top and second group of conductors Oh, Fig. 1).
As to claim 23, (Original): Oh discloses the semiconductor package of claim 21 as discussed above, and further discloses, wherein
the first circuit region comprises a memory circuit ([0032] the first semiconductor chip 100 may be one of memory chips, logic chips, or combinations thereof.”), and wherein
the second circuit region includes an input/output circuit for the memory circuit [0059] “Accordingly, electrical signals may be transmitted to or output from the second chip pads 550 through the outer terminals 400”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. herein referred to as Oh (US 20230132272) in view of Tang et al. herein referred to as Tang, (US 20210334493).
As to claim 4, (Original): Oh teaches the semiconductor package of claim 2. However Oh does not appear to expressly disclose "the length of the first sides ranges from 1µm to 50µm”.
Tang teaches a base substrate in [0054] having a shape of a rectangle with a length of side ranging from 40 µm to 60 µm. Rectangular substrates of this specific geometry balance manufacturing precision with reliable device performance.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the length of the sides of the Oh device such as is in the Tang device, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Furthermore, the Applicant has not shown that the length of the first sides in a range from 1µm to 50µm are novel and would not have been found through routine experimentation.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. herein referred to as Oh, herein referred to as Oh (US 20230132272) in view of Hyun et al., herein referred to as Hyun (US 20190044013)
As to claim 8, (Original): Oh teaches the semiconductor package of claim 1. However, Oh does not appear to expressly disclose "the thickness of the connection conductors is greater than or equal to 1µm”.
Hyun teaches in [0059],a connection connector with a thickness greater than or equal to 1 µm. “For example, the thickness of the connection member 32 can be approximately 30 um to 70 um.” Keeping semiconductor connection members thicker than 1 μm (micrometers) helps minimize electrical contact resistance, reduces parasitic RC delays, and improves structural/thermal stability.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the thickness of the connector in of the Oh device such as is in the Hyun device, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Furthermore, the Applicant has not shown that thickness of the connection conductors greater than or equal to 1µm is novel and would not have been found through routine experimentation.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 20230132272) in view of Nagashima (US 20230091827).
As to claim 9, (Original): Oh discloses the semiconductor package of claim 1.
However, Oh does not appear to expressly disclose "the connection conductors comprise a first group of connection conductors connected to two or more of the first lower pads disposed in the second direction. Connecting components in series directly through their surface-mount pads is a common technique in printed circuit board (PCB) design. Shorter paths mean lower unwanted inductance, which is crucial for high-frequency circuits.
Nagashima teaches in [0093] “In this specification, when it is referred that a first configuration “is electrically connected” to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via a wiring, a semiconductor member, a transistor, or the like. For example, when three transistors are connected in series, even when the second transistor is in OFF state, the first transistor is “electrically connected” to the third transistor.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to design the Oh device connection conductors of a first group of connection conductors connected to two or more of the first lower pads disposed in the second direction such as is in the Nagashima device, so as to make connections in series, placing components end to end saving board real estate, reducing power loss and voltage drops, so as to use an industrially tested and accepted device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
Prosecution Insights