Prosecution Insights
Last updated: October 01, 2026
Application No. 18/673,101

Die and Wafer Level Processing of Laser Diodes and Other Semiconductor Devices on Non-Native Semiconductor Wafers

Non-Final OA §102§103
Filed
May 23, 2024
Priority
Sep 29, 2023 — provisional 63/541,612
Examiner
KIM, SU C
Art Unit
Tech Center
Assignee
Apple Inc.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
66%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
718 granted / 923 resolved
+17.8% vs TC avg
Minimal -12% lift
Without
With
+-11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
31 currently pending
Career history
962
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 923 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5, 7-17, & 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeon et al. (US 20210126045). Regarding claim 1, Yeon discloses that an electronic device, comprising: a set of semiconductor layers defining a set of semiconductor mesas SP1-SP3; a first dielectric abutting 131 the set of semiconductor layers at a perimeter of the set of semiconductor layers SP1-SP3; a second dielectric 140 & 161 on the set of semiconductor mesas; and a set of conductors routed 181 in or on the second dielectric 140 & 161, the set of conductors electrically connected to at least one active device LS defined in at least one semiconductor mesa of the set of semiconductor mesas, the set of conductors configured to route electrical signals to or from the at least one semiconductor mesa, and the set of conductors including a set of hybrid bonding pads on the second dielectric (para. 0057). Reclaim 2, Yeon discloses that the set of semiconductor layers is a first set of semiconductor layers LSx; the set of hybrid bonding pads is a first set of hybrid bonding pads (Fig. 3 & para. 0057); and the electronic device further comprises: a third dielectric 161 on the second dielectric 140; and a second set of conductors 181p routed in or on the third dielectric 161, the second set of conductors including a second set of hybrid bonding pads bonded to the first set of hybrid bonding pads; a semiconductor substrate 210 or 200; and a set of semiconductor structures 245 formed in a second set of semiconductor layers on the semiconductor substrate, the second set of semiconductor layers 245 disposed between the semiconductor substrate and the second set of hybrid bonding pads 285p (Fig. 3). Reclaim 3. The electronic device of claim 2, wherein the first set of semiconductor layers comprise a different set of semiconductor materials than the second set of semiconductor layers. Reclaim 4, Yeon discloses that the first set of semiconductor layers is included in a die diced from a first semiconductor wafer having a first diameter; and the semiconductor substrate and the second set of semiconductor layers is diced from a second semiconductor wafer having a second diameter, the second diameter different from the first diameter. Reclaim 5, Yeon discloses that the at least one active device comprises at least one surface-emitting laser diode LSx (Fig. 3). Reclaim 7, Yeon discloses that the set of conductors comprises a set of conductive vias electrically coupled to the at least one active device (Fig. 3). Reclaim 8, Yeon discloses that the set of semiconductor layers is included in a die diced from a semiconductor wafer having a first diameter; and the set of semiconductor mesas has a pitch that differs from an achievable pitch of a processing toolset for the semiconductor wafer having the first diameter (Fig. 16). Regarding claim 9, Yeon discloses that an electronic device, comprising: a first set of semiconductor layers LS defining a set of semiconductor mesas; a dielectric 131 on the set of semiconductor mesas; and a set of conductors 151, 181, 181p routed in the dielectric, the set of conductors including a set of conductive vias electrically connected to at least one active device defined in at least one semiconductor mesa of the set of semiconductor mesas, the set of conductors configured to route electrical signals to or from the at least one semiconductor mesa (Fig. 3). Reclaim 10, Yeon discloses that a dielectric optical element 191-193 attached to the first set of semiconductor layers, on a side of the set of semiconductor mesas opposite a side of the set of semiconductor mesas including the dielectric, the dielectric optical element defining at least one lens positioned to direct light to or from the at least one active device (Fig. 3). Reclaim 11, Yeon discloses that the dielectric is a first dielectric 131; and the electronic device further includes a second dielectric 110 disposed between the set of semiconductor mesas and the dielectric optical element (Fig. 3). Reclaim 12, Yeon discloses that a multivariate optical element 191-193 attached to the first set of semiconductor layers, on a side of the set of semiconductor mesas opposite a side of the set of semiconductor mesas including the dielectric (Fig. 3). Regarding claim 13, Yeon discloses that an electronic device, comprising: a set of semiconductor layers LS defining a set of semiconductor mesas; a first dielectric 140 & 161 on the set of semiconductor mesas; a first set of conductors 151, 181 181p routed in or on the first dielectric 140, the first set of conductors electrically connected to at least one active device SPx defined in at least one semiconductor mesa of the set of semiconductor mesas, the first set of conductors 151 configured to route electrical signals to or from the at least one semiconductor mesa, and the first set of conductors including a first set of hybrid bonding pads on the first dielectric 140 & 161; a second dielectric 280 or below on the first dielectric 140 & 161; and a second set of conductors 282 routed in or on the second dielectric 280 or below, the second set of conductors including a second set of hybrid bonding pads 185p bonded to the first set of hybrid bonding pads 181p (Fig. 3). Reclaim 14, Yeon discloses that the set of semiconductor layers is a first set of semiconductor layers LS; and the electronic device further comprises: a semiconductor substrate 210; and a set of semiconductor structures formed in a second set of semiconductor layers on the semiconductor substrate, the second set of semiconductor layers disposed between the semiconductor substrate and the second set of hybrid bonding pads (Fig. 3). Reclaim 15, Yeon discloses that the set of semiconductor structures define at least one laser diode driver (LDD) circuit 245, the at least one LDD circuit electrically coupled to the at least one active device via the first set of conductors and the second set of conductors (Fig. 3). Reclaim 16, Yeon discloses that the set of semiconductor layers is included in a first die 100; and the electronic device further comprises: a second die 200; a third dielectric on the second die 200; a third set of conductors routed in or on the third dielectric, the third set of conductors electrically connected to at least one device in the second die and configured to route electrical signals to or from the at least one device, and the third set of conductors including a third set of hybrid bonding pads on the third dielectric; and a fourth set of conductors routed in or on the second dielectric, the fourth set of conductors including a fourth set of hybrid bonding pads bonded to the third set of hybrid bonding pads (Fig. 3). Reclaim 17, Yeon discloses that a fourth dielectric abutting a first perimeter of the first die and a second perimeter of the second die (Fig. 3). Reclaim 19. , Yeon discloses that the set of semiconductor layers is a first set of semiconductor layers; and the electronic device further comprises: a semiconductor substrate; and a first set of semiconductor structures and a second set of semiconductor structures formed in a second set of semiconductor layers on the semiconductor substrate, the second set of semiconductor layers disposed between the semiconductor substrate and the second and fourth sets of hybrid bonding pads, the first set of semiconductor structures defining at least one laser diode driver (LDD) circuit, and the second set of semiconductor structures defining at least one SPAD logic circuit (Fig. 3). Reclaim 20. , Yeon discloses that the at least one active device comprises a surface-emitting laser diode (Fig. 3). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 6 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeon et al. (US 20210126045) in view of Chua et al. (US 20070126010). Reclaim 6, Yeon fails to teach that the at least one active device comprises at least one resonant cavity photodetector (RCPD). However, Chua suggests that resonant cavity photodetector (RCPD) can be utilized with LED devices. Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Yeon with resonant cavity photodetector (RCPD) can be utilized with LED devices as taught by Chua in order to detect performance of LEDs and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Reclaim 18, Yeon fails to teach that that the second die comprises at least one single- photon avalanche detector (SPAD). However, Chua suggests that one single- photon avalanche detector (SPAD) can be utilized with LED devices. Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Yeon with one single- photon avalanche detector (SPAD) can be utilized with LED devices as taught by Chua in order to detect performance of LEDs and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

May 23, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
66%
With Interview (-11.8%)
2y 9m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 923 resolved cases by this examiner. Grant probability derived from career allowance rate.

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