PACKAGE WITH VERTICALLY STACKED DEVICES, AND FABRICATION METHODS THEREOF

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-10 in the reply filed on 7/6/2026 is acknowledged. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/6/2026. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Formosa et al. (20140353775). Regarding Claim 1, in A package, comprising: a first semiconductor device comprising a first functional layer 51/41/2 having a first functional component 50/12/3; and a second semiconductor device 50/12/3 over the first semiconductor device, the second semiconductor device comprising a second functional layer 51/41 /2 having a second functional component 50/12/3, the second functional layer being over a base layer 41, wherein: the base layer is coupled to the second functional layer 51/41/2on a first surface, and is coupled to the first functional layer on a second surface, the first surface and the second surface being on opposite sides of the base layer 41 (Device as shown in Fig 18, has front face vertically stacked MEMS/controller device with through vias connected to the pad in the front face). Regarding Claim 2, in paragraph 0080, an adhesive layer between the first semiconductor device and the second semiconductor device, wherein: a first surface of the adhesive layer is in contact with the base layer; and a second surface of the adhesive layer is in contact with the first functional layer, the first surface and the second surface of the adhesive layer being on opposite sides of the adhesive layer (further see paragraphs 0029, 0047, 0052, 0067) Regarding Claim 3, in paragraphs 0035 and 0070, a molding layer over the first functional layer, and encapsulating the second semiconductor device and the adhesive layer, wherein: the second functional layer is in contact with the molding layer on a first surface and in contact with the base layer on a second surface, the first surface and the second surface of the second functional layer being on opposite sides of the second functional layer. Regarding Claim 4, a routing layer 4/48/58 over the molding layer, the routing layer comprising a conductive routing component encapsulated in an insulating layer; a first conductive via aside from the second semiconductor device and extending in the molding layer; and a second conductive via over the second functional layer and extending in the molding layer. Regarding Claim 5, the first conductive via 44/56/57 is conductively coupled to the conductive routing component and the first functional layer; the second conductive via is conductively coupled to the conductive routing component and the second functional layer; and the second functional component is conductively connected to the first functional component through the first conductive via, the second conductive via, and the conductive routing component (also see paragraph 0043, 0046, 0047, 0056, 0057, 0072-0074, 0084) Regarding Claim 6, another second conductive via 44/56/57 over the second functional layer and extending in the molding layer, the other second conductive via located away from the second conductive layer by a pitch distance, wherein a ratio between the pitch distance and a vertical dimension of the second conductive via is about 2:1 (also see paragraph 0043, 0046, 0047, 0056, 0057, 0072-0074, 0084) Regarding Clain 7, wherein the base layer comprises at least one of a silicon base layer or a molding base layer (see paragraphs 0020 and 0055). Regarding Claim 8, the first semiconductor device comprises another base layer (for example layer 2) , the first functional layer being over the other base layer, and wherein the other base layer comprises at least one of a silicon base layer or a molding base layer. Regarding Claim 9, the first semiconductor device comprises another base layer (for example layer 2), the first functional layer being over the other base layer, and wherein the base layer and the other base layer each comprises a molding base layer. Regarding Claim 10, in paragraphs 0006, 0020, 0023, 0028, 0033, the first functional component comprises a controller component and the second functional component comprises a MEMS component; the first functional component comprises a bulk acoustic wave (BAW) component and the second functional component comprises a low noise amplifier (LNA) component; the first functional component comprises a power amplifier component and the second functional component comprises a power management chip component; or the first functional component comprises a MEMS component and the second functional component comprises a controller component. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 10/7/2026