DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 16 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ker (US 2010/0140659) in view of Murakami (US 2013/0127539).
With regard to claim 1,Ker, in Fig. 7, teaches an integrated circuit (204, paragraph 0024), comprising: a signal connection pad (214); an electrostatic discharge protection circuit (223, paragraph 0025), coupled to the signal connection pad; and an input stage circuit (202), wherein a first input terminal (gate of 210) of the input stage circuit is coupled to the electrostatic discharge protection circuit, and the input stage circuit comprises: a load circuit (208); a current source circuit (as seen in Fig. 5); a first input transistor (210), wherein a control terminal (gate of 210) of the first input transistor is coupled to the electrostatic discharge protection circuit, a first terminal (drain of 210) of the first input transistor is coupled to the load circuit (208), and a second terminal (source of 210) of the first input transistor is coupled to the current source circuit (as seen in Fig. 5).
Ker does not teach an impedance circuit, wherein a first terminal of the impedance circuit is coupled to a body of the first input transistor, and a second terminal of the impedance circuit is coupled to a first voltage.
Murakami, in Figure 5, teaches a circuit similar to Okushima wherein the circuit is an integrated circuit (Abstract), comprising: a signal connection pad (101); a high voltage protection circuit (103), coupled to the signal connection pad; and an input stage circuit (104), wherein a first input terminal of the input stage circuit is coupled to the electrostatic discharge protection circuit, and the input stage circuit comprises: a load circuit (112); a current circuit (113); a first input transistor (111), wherein a control terminal (gate) of the first input transistor is coupled to the protection circuit, a first terminal (drain) of the first input transistor is coupled to the load circuit, and a second terminal (source) of the first input transistor is coupled to the current circuit (113); and an impedance circuit (114’), wherein a first terminal of the impedance circuit is coupled to a body of the first input transistor, and a second terminal of the impedance circuit is coupled to a first voltage (ground).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ker with Murakami, by coupling the bodies of the transistors of Ker to ground through an impedance circuit as taught by Murakami, for the purpose of reducing the capacitance seen at the gate of the input transistors, thus improving the frequency that the input circuit can operate at and reducing the noise factor of the input circuit (Murakami paragraph 0049).
With regard to claims 2-8, 16 & 17, Ker in view of Murakami discloses the device of claim 1, and further discloses that the input stage circuit further comprises: a second input transistor (Ker, 212), wherein the second input transistor and the first input transistor are an input transistor pair of the input stage circuit (Ker, paragraph 0005), a control terminal (Ker, gate of 212) of the second input transistor serves as a second input terminal of the input stage circuit to be coupled to the electrostatic discharge protection circuit (Ker, 226), a first terminal (Ker, drain of 212) of the second input transistor is coupled to the load circuit (Ker, 208), a second terminal (Ker, source of 212) of the second input transistor is coupled to the current source circuit (as seen in Fig. 5 of Ker), and a body of the second input transistor is coupled to the first terminal of the impedance circuit (Murakami teaches that the body of the resistor 111 is coupled to the impedance as it would have been obvious to couple the impedance to the body of both input transistors) (re claim 2), wherein the first input transistor is an N-type transistor (as seen in Fig 3 Murakami), the second terminal of the impedance circuit is coupled to a substrate of the integrated circuit (Murakami, through 113 and ground), the substrate of the integrated circuit is coupled to the first voltage (ground), and the first voltage is a reference voltage VSS (re claim 3), wherein the first input transistor is disposed in a first type well of (P-well of Murakami) the integrated circuit (Fig. 7 of Murakami), the first type well is disposed in a second type deep well (Deep N-well of Murakami) of the integrated circuit, the second type deep well is disposed in a substrate (P-sub of Murakami) of the integrated circuit, the substrate is a first type substrate (P-type), and the second type deep well isolates the body of the first input transistor from the substrate of the integrated circuit (re claim 4), wherein the first type well is a P-type well, the second type deep well is an N-type deep well, the substrate is a P-type substrate, and the P-type substrate is coupled to a reference voltage VSS (as seen in Figs. 5 & 7 of Murakami) (re claim 5), wherein the load circuit comprises: a resistor (Murakami, 112), wherein a first terminal of the resistor is coupled to a second voltage (VDD, Ker), and a second terminal of the resistor is coupled to the first terminal of the first input transistor (drain of 111, Ker) (re claim 6), wherein the current source circuit comprises: a current source, coupled to the second terminal of the first input transistor (as seen in Fig. 5) (re claim 7), wherein the impedance circuit comprises: a resistor, wherein a first terminal of the resistor is coupled to the body of the first input transistor, and a second terminal of the resistor is coupled to the first voltage (as seen in Fig. 5 of Murakami) (re claim 8), further comprising: an electrostatic discharge enhanced-protection circuit, coupled to the electrostatic discharge protection circuit and the input stage circuit (the ESD protection circuit 100 of Ker enhances the ESD protection diodes 220 & 224) (re claim 16), wherein the electrostatic discharge enhanced-protection circuit comprises: an electrostatic discharge protection transistor (STSCR 200 of Ker comprises transistors), wherein a first terminal of the electrostatic discharge protection transistor is coupled to the electrostatic discharge protection circuit and the control terminal of the first input transistor (as seen in Fig. 6 of Ker), a second terminal and a control terminal of the electrostatic discharge protection transistor are coupled to a power rail of the integrated circuit (through trigger circuit 250), and the power rail is coupled to a power connection pad of the integrated circuit (re claim 17).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ker in view of Murakami as applied to claim 1 above, and further in view of Olson (US 2014/0171010).
With regard to claim 9, Ker in view of Murakami teaches the device of claim 1 and further teaches that a first terminal of the impedance is coupled to the body of the first input transistor, and a second terminal of the impedance is coupled to the first voltage.
Ker in view of Murakami does not teach that the impedance circuit comprises: an inductor, wherein a first terminal of the inductor is coupled to the body of the first input transistor, and a second terminal of the inductor is coupled to the first voltage.
Olson, in Figure 1A, teaches a transistor (110) with an impedance element (130) coupled between the bulk of the MOSFET and ground potential. It is further taught that the impedance circuit comprises: an inductor (paragraph 0044), wherein a first terminal of the inductor is coupled to the body of the first input transistor (through switch 120), and a second terminal of the inductor is coupled to the first voltage (as seen in Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ker in view of Murakami with Olson, by forming the impedance of Murakami as an inductor as taught by Olson, for the purpose of allowing the body of the MOSFET to float relative to AC but to be connected to ground relative to DC.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ker in view of Murakami as applied to claim 1 above, and further in view of Brown (US 2010/0103571).
With regard to claim 10, Ker in view of Murakami teaches the device of claim 1 wherein the electrostatic discharge protection circuit comprises: a power clamping circuit (Ker, 200), wherein a first terminal of the power clamping circuit is coupled to a first power rail (VDD) of the integrated circuit, the first power rail is coupled to a first power connection pad of the integrated circuit, a second terminal of the power clamping circuit is coupled to a second power rail (VSS) of the integrated circuit, and the second power rail is coupled to a second power connection pad of the integrated circuit; a first diode (224), wherein a first terminal of the first diode is coupled to the signal connection pad, and a second terminal of the first diode is coupled to the second power rail.
Ker in view of Murakami does not teach an alternating current coupling capacitor, wherein a first terminal of the alternating current coupling capacitor is coupled to the signal connection pad and the first terminal of the first diode, and a second terminal of the alternating current coupling capacitor is coupled to the control terminal of the first input transistor.
Brown, in Figure 5, teaches an input transistor (35) similar to Ker wherein a gate of the transistor is coupled to ESD protection diodes (32). It is further taught that the device comprises an alternating current coupling capacitor (36), wherein a first terminal of the alternating current coupling capacitor is coupled to a signal connection pad (38) and the first terminal of the first diode (32), and a second terminal of the alternating current coupling capacitor is coupled to the control terminal of the first input transistor (35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ker in view of Murakami with Brown, by incorporating the coupling capacitor of Brown into the circuit of Ker, for the purpose of blocking DC current from the gate of the transistor.
With regard to claims 11 & 12, Ker in view of Murakami and Brown discloses the device of claim 10, and further discloses that the first power rail is configured to transmit a system voltage VDD, and the second power rail is configured to transmit a reference voltage VSS (as seen in Fig. 6 of Ker) (re claim 11), wherein the electrostatic discharge protection circuit further comprises: a second diode (Ker, 220) wherein a first terminal of the second diode is coupled to the first power rail, and a second terminal of the second diode is coupled to the signal connection pad (re claim 12).
Claims 13 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ker in view of Murakami and Brown as applied to claim 10 above, and further in view of Ma (US 2005/0122644).
With regard to claim 13, Ker in view of Murakami and Brown teaches the device of claim 10.
Ker in view of Murakami and Brown does not teach the electrostatic discharge protection circuit further comprises: a diode string, comprising a plurality of diodes connected in series, wherein a first terminal of the diode string is coupled to the signal connection pad and the first terminal of the alternating current coupling capacitor, and a second terminal of the diode string is coupled to the second power rail.
Ma, in Figure 2, teaches an ESD protection circuit coupled to an input pad wherein a first ESD protection diode (12) is coupled between the pad and ground. It is further taught that the electrostatic discharge protection circuit further comprises: a diode string (10), comprising a plurality of diodes connected in series, wherein a first terminal of the diode string is coupled to the signal connection pad, and a second terminal of the diode string is coupled to the second power rail.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ker in view of Murakami and Brown with Ma, by incorporating the diode string of Ma into the circuit of Ker, for the purpose of providing bi-direction ESD protection ground the ground terminal to the signal pad.
With regard to claim 14, Ker in view of Murakami, Brown & Ma discloses the device of claim 13, and further discloses a cathode of the first diode is coupled to the signal connection pad, an anode of the first diode is coupled to the second power rail, an anode of the diode string is coupled to the signal connection pad, and a cathode of the diode string is coupled to the second power rail (as seen in Fig. 2 of Ma).
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Ker in view of Murakami as applied to claim 1 above, and further in view of Kajiwara (US 2004/0061554).
With regard to claim 15, Ker in view of Murakami teaches the device of claim 1.
Ker in view of Murakami does not teach a bias circuit, coupled to the control terminal of the first input transistor.
Kajiwara, in Figure 1A, teaches an input circuit comprising a differential pair of transistors (Q1 & Q2). It is further taught that the device comprises a bias circuit (R1, R2 & Vbias), coupled to the control terminal of the input transistors (paragraph 0008).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ker in view of Murakami with Kajiwara, by implementing the device of Ker with a gate bias circuit, for the purpose of ensuring that the gate of the transistor does not float if an input terminal is not connected.
Conclusion
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/Scott Bauer/Primary Examiner, Art Unit 2838