DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 5/30/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (currently Claims 1-18) in the reply filed on 7/29/2026 is acknowledged.
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/29/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1-18 are objected to because of the following informalities:
Re Claim 1, “hardness of the second encapsulation layer” in line 13, “hardness of the first encapsulation layer” in lines 13-14, and “hardness of the third encapsulation layer” in line 14 should be “a hardness of the second encapsulation layer”, “a hardness of the first encapsulation layer”, and “a hardness of the third encapsulation layer”, respectively, for grammatical correctness and clarity.
Re Claim 6, “thickness of the second encapsulation layer” in lines 1-2 and “thickness of the first encapsulation layer” in line 2 should be “a thickness of the second encapsulation layer” and “a thickness of the first encapsulation layer”, respectively, for grammatical correctness and clarity.
Re Claim 8, “thickness of the third encapsulation layer” in lines 1-2 and “thickness of the first encapsulation layer” in line 2 should be “a thickness of the third encapsulation layer” and “a thickness of the first encapsulation layer”, respectively, for grammatical correctness and clarity.
Re Claim 9, “thickness of the third encapsulation layer” in lines 1-2 and “thickness of the second encapsulation layer” in line 2 should be “a thickness of the third encapsulation layer” and “a thickness of the second encapsulation layer”, respectively, for grammatical correctness and clarity.
In Re Claims 2-18, they inherit the objection to Claim 1 due to their dependence from Claim 1. In Re Claims 16 and 18, they inherit the objections to Claims 6 and 8, respectively, due to their dependences from Claims 6 and 8.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishimura (US 2022/0115284 A1).
Re Claim 1, Nishimura discloses a semiconductor module (FIG. 3; [0046]-[0051]), comprising:
a laminated substrate (20; [0022]);
multiple semiconductor chips (40; [0023]) provided on the laminated substrate (20; [0023]);
a bonding wire (27; [0029]) connected to the multiple semiconductor chips (40; [0029]);
a housing (10; [0026]) which accommodates the multiple semiconductor chips (40; [0026]), the bonding wire (27; [0026]), and the laminated substrate (20; [0026]);
a first encapsulation layer (44; [0046]) which covers the multiple semiconductor chips (40; [0046]), the bonding wire (27; [0046]), and the laminated substrate (20) inside the housing (10; [0046]);
a second encapsulation layer (46; [0046]) provided on the first encapsulation layer (44; [0046]); and
a third encapsulation layer (42; [0047]) provided on the second encapsulation layer (46; [0047], on the bottom of), wherein
the first encapsulation layer (44) is filled inside the housing (10) up to a position higher than an upper surface of the bonding wire (27; [0046]), and
hardness of the second encapsulation layer (46) is greater than a hardness of the first encapsulation layer (44; [0048]) and less than hardness of the third encapsulation layer (42; [0047]-[0048]).
Re Claim 3, Nishimura discloses the semiconductor module according to Claim 1, while further disclosing wherein a film thickness of the first encapsulation layer (44) is 3.5 mm and 4.5 mm or less ([0050]).
Re Claim 4, Nishimura discloses the semiconductor module according to Claim 1, while further disclosing wherein the first encapsulation layer (44) contains silicone gel material ([0043]) or fluorogel material.
Re Claim 6, Nishimura discloses the semiconductor module according to Claim 1, while further disclosing wherein thickness of the second encapsulation layer (46) is thinner than thickness of the first encapsulation layer (44; [0050], FIG. 3).
Re Claim 9, Nishimura discloses the semiconductor module according to Claim 1, while further disclosing wherein thickness of the third encapsulation layer (42) is equal to thickness of the second encapsulation layer (46; [0046], in direction parallel to top surface of 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Miyanagi (US 2015/0187674 A1), in view of Nakagawa et al (US 2016/0126923 A1, hereafter Nakagawa).
Re Claim 1, Miyanagi discloses a semiconductor module (FIG. 2; [0042]-[0043]), comprising:
a laminated substrate (2, 3, 4; [0010]);
multiple semiconductor chips (1; [0008]) provided on the laminated substrate (2, 3, 4; [0008]);
a bonding wire (6; [0009]) connected to the multiple semiconductor chips (1; [0009]);
a housing (7; [0011]) which accommodates the multiple semiconductor chips (1; [0011]), the bonding wire (6; [0011]), and the laminated substrate (2, 3, 4; [0011]);
a first encapsulation layer (A; [0019]) which covers the multiple semiconductor chips (1; [0019]), the bonding wire (6; [0019]), and the laminated substrate (2, 3, 4) inside the housing (7; [0019]);
a second encapsulation layer (B; [0019]) provided on the first encapsulation layer (A; [0019]); and
a third encapsulation layer (8; [0040]) provided on the second encapsulation layer (B; [0040]), wherein
the first encapsulation layer (A) is filled inside the housing (7) up to a position higher than an upper surface of the bonding wire (6; [0019]), and
hardness of the second encapsulation layer (B) is greater than a hardness of the first encapsulation layer (A; [0020]).
Miyanagi does not explicitly disclose wherein hardness of the second encapsulation layer (B) is less than hardness of the third encapsulation layer (8).
However, Nakagawa teaches a semiconductor module (FIG. 9; [0132]-[0140]) wherein an encapsulation layer/lid (530; [0138]) is made out of metal(s) ([0030], for example kovar). Thus, the lid of Miyanagi being kovar would render the hardness of the second encapsulation layer (Miyanagi: B, being made of resin with a filler of aluminum) as less than hardness of the third encapsulation layer (Miyanagi: 8, being made of kovar, which is harder than aluminum by itself).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Miyanagi with the limitations taught by Nakagawa to use a metal alloy like kovar for the third encapsulation layer (Miyanagi: 8) as a functionally equivalent means of predictably preventing introduction of moisture/foreign contaminants into the device as taught by Nakagawa ([0138]).
Re Claim 8, Miyanagi and Nakagawa teach the semiconductor module according to Claim 1, while Miyanagi further teaches wherein thickness of the third encapsulation layer (8) is thinner than thickness of the first encapsulation layer (A; [0011], FIG. 2).
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Miyanagi and Nakagawa, as applied to Claim 1, further in view of Hartung et al (US 2018/0033711 A1, hereafter Hartung).
Re Claim 2, Miyanagi and Nakagawa teach the semiconductor module according to Claim 1, while they do not explicitly disclose wherein a distance between an upper end of the first encapsulation layer (Miyanagi: A) and an upper end of the bonding wire (Miyanagi: 6) is 0.5 mm or more and 1.5 mm or less.
However, Hartung teaches a semiconductor module (FIG. 2C; [0053]-[0065]) comprising wherein a distance between an upper end of the first encapsulation layer (51; [0054]) and an upper end of the bonding wire (top surface of 3 at 32, which would be an “upper end” in the vertical direction at that location; [0037]) is 0.5 mm or more and 1.5 mm or less ([0049]).
Looking at FIG. Z1 below, the lowest point of the upper end of the bonding wire (Miyanagi: 6) is about halfway through the first encapsulation layer (Miyanagi: A), the first encapsulation layer (Miyanagi: A) intended to cover the bonding wire (Miyanagi: 6; [0042]). Incorporating half of Hartung’s max first encapsulation layer thickness at 1.05 mm results in a thickness of 0.525 mm, which is in the claimed limitation’s range.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 1 with the limitations taught by Hartung to specify the first encapsulation layer’s (Miyanagi: A) thickness (and therefore distance between the first encapsulation layer’s (Miyanagi: A) upper end and an upper end of the bonding wire (Miyanagi: 6) as a predictable means of completely embedding the bonding wire (Miyanagi: 6) in the first encapsulation layer (Miyanagi: A) as taught by Hartung ([0055]).
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FIG. Z1: Annotated version of FIG. 2 of Miyanagi
Re Claim 5, Miyanagi and Nakagawa teach the semiconductor module according to Claim 1, while they do not explicitly disclose wherein the second encapsulation layer (Miyanagi: B) contains silicone elastomer material.
However, Hartung teaches a semiconductor module (FIG. 2C; [0053]-[0065]) comprising wherein the second encapsulation layer (51; [0044], “second” layer being harder layer between 51, 52 when related to Miyanagi) contains silicone elastomer material ([0046]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 1 with the limitations taught by Hartung to substitute in silicone elastomer as the resin material as a functionally equivalent means of providing a base for a relatively hard encapsulation layer whose thermal properties are modified by filler material to improve device performance as taught by Hartung ([0044]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, as applied to Claim 1, in view of Hartung.
Re Claim 7, Nishimura discloses the semiconductor module according to Claim 1, but they do not explicitly disclose wherein the third encapsulation layer (42) contains silicone elastomer material.
However, Hartung teaches a semiconductor module (FIG. 2C; [0053]-[0065]) comprising wherein the third encapsulation layer (51; [0044], “third” layer being bottom hard layer in this case when related to Nishimura) contains silicone gel material ([0046]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 1 with the limitations taught by Hartung to substitute in silicone gel as the resin material as a functionally equivalent means of providing a base for a relatively hard encapsulation layer whose thermal properties are modified by filler material to improve device performance as taught by Hartung ([0044]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, as applied to Claim 1, in view of Redline et al (US 2021/0387987 A1, hereafter Redline).
Re Claim 10, Nishimura discloses the semiconductor module according to Claim 1, but they do not explicitly disclose wherein a coefficient of thermal expansion (CTE) of the second encapsulation layer (46) is less than a coefficient of thermal expansion of the first encapsulation layer (44), and greater than a coefficient of thermal expansion of the third encapsulation layer (42).
However, Redline teaches wherein epoxy resin has a high CTE of ~55 ppm/degrees Celsius, while silica as an inorganic filler possesses a CTE between ~6-8 ppm/degrees Celsius ([0005]).
Therefore a coefficient of thermal expansion of the second encapsulation layer (Nishimura: 46) is less than a coefficient of thermal expansion of the first encapsulation layer (Nishimura: 44; [0047]), and greater than a coefficient of thermal expansion of the third encapsulation layer (Nishimura: 42; [0047]), by nature of their relative inorganic filler percentages (Nishimura: [0047], the “first” encapsulation layer 44 has the highest inorganic filler content, the “second” encapsulation layer 46 has the second highest, and the “third” encapsulation layer 42 has the lowest).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 1 with the limitations taught by Redline to specify the relative CTE values of the encapsulation layers as a predictable innate result of the degree of inorganic filler specified by Nishimura ([0047]) and as taught by Redline ([0005]).
Claims 11, 13-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura, as applied to Claims 1, 3-4, and 6, respectively, in view of Kanai et al (US 2017/0278771 A1, hereafter Kanai).
Re Claim 11, Nishimura discloses the semiconductor module according to Claim 1, but does not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (44), and the multiple semiconductor chips (40), the bonding wire (27) and the laminated substrate (20).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 1 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Re Claim 13, Nishimura discloses the semiconductor module according to Claim 3, but does not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (44), and the multiple semiconductor chips (40), the bonding wire (27) and the laminated substrate (20).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 3 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Re Claim 14, Nishimura discloses the semiconductor module according to Claim 4, but does not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (44), and the multiple semiconductor chips (40), the bonding wire (27) and the laminated substrate (20).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 4 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Re Claim 16, Nishimura discloses the semiconductor module according to Claim 6, but does not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (44), and the multiple semiconductor chips (40), the bonding wire (27) and the laminated substrate (20).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 6 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Miyanagi, Nakagawa, and Hartung, as applied to Claims 2 and 5, respectively, further in view of Kanai.
Re Claim 12, Miyanagi, Nakagawa, and Hartung teach the semiconductor module according to Claim 2, but they do not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (Miyanagi: A), and the multiple semiconductor chips (Miyanagi: 1), the bonding wire (Miyanagi: 6) and the laminated substrate (Miyanagi: 2, 3, 4).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 2 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Re Claim 15, Miyanagi, Nakagawa, and Hartung teach the semiconductor module according to Claim 5, but they do not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (Miyanagi: A), and the multiple semiconductor chips (Miyanagi: 1), the bonding wire (Miyanagi: 6) and the laminated substrate (Miyanagi: 2, 3, 4).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 5 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura and Hartung, as applied to Claim 7, further in view of Kanai.
Re Claim 17, Nishimura and Hartung teach the semiconductor module according to Claim 7, but they do not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (Nishimura: 44), and the multiple semiconductor chips (Nishimura: 40), the bonding wire (Nishimura: 27) and the laminated substrate (Nishimura: 20).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 7 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Miyanagi and Nakagawa, as applied to Claim 8, further in view of Kanai.
Re Claim 18, Miyanagi and Nakagawa teach the semiconductor module according to Claim 8, but they do not explicitly disclose the module comprising a primer layer provided between the first encapsulation layer (Miyanagi: A), and the multiple semiconductor chips (Miyanagi: 1), the bonding wire (Miyanagi: 6) and the laminated substrate (Miyanagi: 2, 3, 4).
However, Kanai discloses a semiconductor module (FIG. 3; [0056]-[0068]) comprising a primer layer (9; [0056]) provided between the first encapsulation layer (8; [0056]), and the multiple semiconductor chips (1), the bonding wire (13; [0056]) and the laminated substrate (2; [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor module according to Claim 8 with the limitations taught by Kanai to use a primer layer (Kanai: 9) to increase adhesion between the resin and metal/case elements as taught by Kanai ([0007]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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