DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for priority to U. S. Provisional Patent Application No. 63/545,736, filed on 10/25/2023.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 10/4/2024 and 4/21/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restriction
It has been acknowledged that the applicant has elected without traverse Embodiment 1 by cancelling claims 2 (Embodiments 2-4) per the response dated on 7/7/2026. Currently claims 1-5, 11-12, and 15-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakai (US 2016/0163800 A1).
Regarding claim 1, Sakai teaches a moisture resistant semiconductor device (MOSFET 100, Fig. 1, [0018] and [0021]: “With this configuration, a semiconductor device having a high breakdown voltage and high moisture resistance can be provided”) comprising:
a substrate (semiconductor layer 10, Fig. 1, [0035]);
a plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1, [0035]) in the substrate (semiconductor layer 10, Fig. 1) of the semiconductor device (MOSFET 100, Fig. 1), wherein the plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1) are laterally adjacent to an active region (element region IR, Fig. 1, [0034]) of the semiconductor device (MOSFET 100, Fig. 1);
a first insulating layer (insulating film 15, Fig. 1, [0051]) which overlays the plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1) and the substrate (semiconductor layer 10, Fig. 1);
a trench (trench 5, Fig. 1, [0027] and [0036]) into the substrate (semiconductor layer 10, Fig. 1) located laterally beyond an edge of the plurality of terminations (right edge of JTE region 2, guard ring regions 3, and field stop region 4 in Fig. 1);
a contact layer (interlayer insulating film 71 including contacts source wire 20, gate wire 21, and gate electrode 17; Fig. 1, [0045]) which overlays the first insulating layer (insulating film 15, Fig. 1);
a second insulating layer (lower film of protecting film 1, Fig. 1 (layers of protecting film 1 are not shown in Fig. 1), [0037]: “protecting film 1 is formed as a multilayered film. In this case, protecting film 1 is formed in contact with interlayer insulating film 71. A material forming a lower film is SiO2, for example, and a material forming an upper film formed on the lower film is SiN, for example.”) which overlays the contact layer (interlayer insulating film 71, Fig. 1), the second insulating layer (lower film of protecting film 1, Fig. 1) overlays the trench (trench 5, Fig. 1); and
a third insulating layer (upper film of protecting film 1, Fig. 1) which overlays the second insulating layer (lower film of protecting film 1, Fig. 1).
Regarding claim 2, Sakai teaches the semiconductor device of claim 1, wherein the first insulating layer (insulating film 15, Fig. 1) comprises a field oxide layer ([0051]: “insulating film 15 made of silicon dioxide”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) as applied to claims 1-2 above, and further in view of Hiyoshi-Embodiment 1 (US 2016/0013137 A1, Embodiment in Fig. 12).
Regarding claim 3, while Sakai teaches the semiconductor device of claim 1,
Sasaki does not teach that the contact layer comprises an oxynitride layer or a silicon oxynitride layer.
Hiyoshi-Embodiment 1, however, teaches a moisture resistant semiconductor device (semiconductor device 102, Fig. 12, [0130]) wherein
the contact layer (second insulating film 22 which is analogous to the contact layer of Sasaki in that it contains contacts (source electrode 16 and the via contacting the source electrode), Fig. 12) comprises an oxynitride layer or a silicon oxynitride layer ([0044]: “second insulating film 22 includes at least one of silicon nitride (SiN) and silicon oxynitride (SiON).”).
Hiyoshi-Embodiment 1 further teaches that silicon oxynitride (SiON) have higher moisture resistance than silicon dioxide ([0062]-[0063]), and therefore using a contact layer (second insulating film 22) made of silicon oxynitride (SiON) blocks the entry of moisture to the underlying first insulating layer ([0062]), which is silicon oxide in both Sasaki and Hiyoshi-Embodiment 1. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the material of the contact layer in the semiconductor device of Sasaki to be silicon oxynitride (SiON), as taught by Hiyoshi-Embodiment 1, to be able to prevent moisture to reach the first insulating layer.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) as applied to claims 1-2 above, and further in view of Hiyoshi-Embodiment 2 (US 2016/0013137 A1, Embodiment in Fig. 16).
Regarding claim 4, while Sasaki teaches the semiconductor device of claim 1,
Sasaki does not teach that the second insulating layer comprises a nitride layer.
Hiyoshi-Embodiment 2, however, teaches a moisture resistant semiconductor device (semiconductor device 201, Fig. 16, [0130]), wherein the second and third insulating layers (second insulating layer 22 is analogous to the second and third insulating layers of Sasaki in terms of covering the trench), are formed from “at least one of silicon nitride (SiN) and silicon oxynitride (SiON)” ([0044]), and therefore the second insulating layer comprises a nitride layer.
Hiyoshi-Embodiment 2 further discloses that “by making the upper layer (second insulating film 22) of SiN and SiON having high moisture resistance the entry of moisture into element region DR can be suppressed” ([0045]), as “SiO2 has slightly low moisture resistance and has a probability of allowing moisture to permeate therethrough” ([0043]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the protecting film 1 of Sasaki (see Fig. 1 of Sasaki and claim 1 rejection above) with a protective film formed from SiN and SiON, as taught by Hiyoshi-Embodiment 2, instead of SiO2 and SiN, which would further improve the moisture resistance of the semiconductor device. Thus, the combination of Sasaki and Hiyoshi-Embodiment 2 meets the limitations of claim 4.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) as applied to claims 1-2 above, and further in view of Ebihara (US 2024/0274655 A1).
Regarding claim 5, while Sasaki teaches the semiconductor device of claim 1,
Sasaki does not teach that the third insulating layer comprises a polyimide layer.
Ebihara, on the other hand, teaches a semiconductor device (semiconductor device, Fig 12) with a multilayer surface protection film (surface protection film 25, Fig. 12, [0093]) analogous to the multilayer surface protection film (protecting film 1) of Sasaki which forms the second and third insulating layers (see claim 1 rejection above). Ebihara further teaches that organic material such as polyimide or an inorganic material such as silicon nitride can be used as the material of the surface protection film 25. Considering that the third insulating layer of Sasaki is SiN ([0037]: “protecting film 1 is formed as a multilayered film. In this case, protecting film 1 is formed in contact with interlayer insulating film 71. A material forming a lower film is SiO2, for example, and a material forming an upper film formed on the lower film is SiN, for example.”), and according to the teachings of Ebihara, polyimide is a known equivalent of SiN as a protecting film. Selection of a known material for the same purpose is prima facie obvious (see MPEP 2144.06), and therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki such that the third insulating layer comprises polyimide.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) in view of Hiyoshi-Embodiment 2 (US 2016/0013137 A1, Embodiment in Fig. 16).
Regarding claim 11, Sakai teaches a moisture resistant semiconductor device (MOSFET 100, Fig. 1, [0018] and [0021]: “With this configuration, a semiconductor device having a high breakdown voltage and high moisture resistance can be provided”) comprising:
a substrate (semiconductor layer 10, Fig. 1, [0035]);
a plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1, [0035]) in the substrate (semiconductor layer 10, Fig. 1) of the semiconductor device (MOSFET 100, Fig. 1), wherein the plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1) are laterally adjacent to an active region (element region IR, Fig. 1, [0034]) of the semiconductor device (MOSFET 100, Fig. 1);
a first insulating layer (insulating film 15, Fig. 1, [0051]) which overlays the plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1) and the substrate (semiconductor layer 10, Fig. 1);
a recess (trench 5, Fig. 1, [0027] and [0036]) into the substrate (semiconductor layer 10, Fig. 1) located laterally beyond an edge of the plurality of terminations (right edge of JTE region 2, guard ring regions 3, and field stop region 4 in Fig. 1);
a contact layer (interlayer insulating film 71 including contacts source wire 20, gate wire 21, and gate electrode 17; Fig. 1, [0045]) which overlays the first insulating layer (insulating film 15, Fig. 1);
a second insulating layer (lower film of protecting film 1, Fig. 1 (layers of protecting film 1 are not shown in Fig. 1), [0037]: “protecting film 1 is formed as a multilayered film. In this case, protecting film 1 is formed in contact with interlayer insulating film 71. A material forming a lower film is SiO2, for example, and a material forming an upper film formed on the lower film is SiN, for example.”) which overlays the contact layer (interlayer insulating film 71, Fig. 1) and which overlays the recess (trench 5, Fig. 1); and
a third insulating layer (upper film of protecting film 1, Fig. 1) which overlays the second insulating layer (lower film of protecting film 1, Fig. 1).
Sakai, however, does not teach that the semiconductor device comprises
a plurality of recesses into the substrate located laterally beyond an edge of the plurality of terminations; and
the second insulating layer overlays the plurality of recesses.
Hiyoshi-Embodiment 2, on the other hand, teaches a moisture resistant semiconductor device (semiconductor device 201, Fig. 16, [0141]), comprising
a plurality of recesses (first step portion ST1, second step portion ST2, and third step portion ST3, Fig. 16, [0110]) into the substrate (semiconductor layer 10, Fig. 16, [0113]) located laterally beyond an edge of the plurality of terminations (plurality of guard ring portions 3a to 3e, Fig. 16, [0117]); and
the second insulating layer (second insulating film 22, Fig. 16, [0120]: second insulating film 22 is analogous to the protective film 1 of Sakai) overlays the plurality of recesses (first step portion ST1, second step portion ST2, and third step portion ST3, Fig. 16).
Hiyoshi-Embodiment 2 further discloses that “by providing the plurality of step portions in this manner, the occurrence of cracking that reaches element region DR or the occurrence of serious chipping (debris) can be more reliably reduced.” ([0110]), where DR is the element region corresponding the active and termination regions. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor device of Sakai to include a plurality of recesses, instead of only one recess, into the substrate located laterally beyond an edge of the plurality of terminations such that the second insulating layer overlays the plurality of recesses, as taught by Hiyoshi-Embodiment 2, to be able to reliably reduce reliably the cracking or chipping reaching the active region. Thus, the combination of Sakai and Hiyoshi-Embodiment 2 meets all the limitations of claim 11.
Regarding claim 12, Sakai in view of Hiyoshi-Embodiment 2 teaches the semiconductor device of claim 11, wherein
Sakai further teaches that the first insulating layer (insulating film 15, Fig. 1) comprises a field oxide layer ([0051]: “insulating film 15 made of silicon dioxide”).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) in view of Hiyoshi-Embodiment 2 (US 2016/0013137 A1, Embodiment in Fig. 16) as applied to claims 11-12 above, and further in view of Ebihara (US 2024/0274655 A1).
Regarding claim 15, while Sasaki in view of Hiyoshi-Embodiment-2 teaches the semiconductor device of claim 11,
neither Sasaki nor Hiyoshi-Embodiment-2 teaches that the third insulating layer comprises a polyimide layer.
Ebihara, on the other hand, teaches a semiconductor device (semiconductor device, Fig 12) with a multilayer surface protection film (surface protection film 25, Fig. 12, [0093]) analogous to the multilayer surface protection film (protecting film 1) of Sasaki in view of Hiyoshi-Embodiment 2 which forms the second and third insulating layers (see claim 1 rejection above). Ebihara further teaches that organic material such as polyimide or an inorganic material such as silicon nitride can be used as the material of the surface protection film 25. Considering that the third insulating layer of Sasaki in view of Hiyoshi-Embodiment 2 is SiN ([0037]: “protecting film 1 is formed as a multilayered film. In this case, protecting film 1 is formed in contact with interlayer insulating film 71. A material forming a lower film is SiO2, for example, and a material forming an upper film formed on the lower film is SiN, for example.”) , and according to the teachings of Ebihara, polyimide is a known equivalent of SiN as a protecting film. Selection of a known material for the same purpose is prima facie obvious (see MPEP 2144.06), and therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki in view of Hiyoshi-Embodiment 2 such that the third insulating layer comprises polyimide.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) in view of Hiyoshi-Embodiment 1 (US 2016/0013137 A1, Embodiment in Fig. 12).
Regarding claim 16, Sakai teaches a moisture resistant semiconductor device (MOSFET 100, Fig. 1, [0018] and [0021]: “With this configuration, a semiconductor device having a high breakdown voltage and high moisture resistance can be provided”) comprising:
a substrate (semiconductor layer 10, Fig. 1, [0035]);
a plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1, [0035]) in the substrate (semiconductor layer 10, Fig. 1) of the semiconductor device (MOSFET 100, Fig. 1), wherein the plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1) are laterally adjacent to an active region (element region IR, Fig. 1, [0034]) of the semiconductor device (MOSFET 100, Fig. 1);
a first insulating layer (insulating film 15, Fig. 1, [0051]) which overlays the plurality of terminations (JTE region 2, guard ring regions 3, and field stop region 4; Fig. 1) and the substrate (semiconductor layer 10, Fig. 1);
a recess (trench 5, Fig. 1, [0027] and [0036]) into the substrate (semiconductor layer 10, Fig. 1) located laterally beyond an edge of the plurality of terminations (right edge of JTE region 2, guard ring regions 3, and field stop region 4 in Fig. 1);
a contact layer (interlayer insulating film 71 including contacts source wire 20, gate wire 21, and gate electrode 17; Fig. 1, [0045]) which overlays the first insulating layer (insulating film 15, Fig. 1);
a second insulating layer (lower film of protecting film 1, Fig. 1 (layers of protecting film 1 are not shown in Fig. 1), [0037]: “protecting film 1 is formed as a multilayered film. In this case, protecting film 1 is formed in contact with interlayer insulating film 71. A material forming a lower film is SiO2, for example, and a material forming an upper film formed on the lower film is SiN, for example.”) which overlays the contact layer (interlayer insulating film 71, Fig. 1); and
a third insulating layer (upper film of protecting film 1, Fig. 1) which overlays the second insulating layer (lower film of protecting film 1, Fig. 1).
Sakai, however, does not teach that the semiconductor device comprises
a plurality of recesses into the substrate located laterally beyond an edge of the plurality of terminations; and
the contact layer overlays the plurality of recesses.
Hiyoshi-Embodiment 1, on the other hand, teaches a moisture resistant semiconductor device (semiconductor device 102, Fig. 12, [0130]), comprising
a plurality of recesses (first step portion ST1, second step portion ST2, and third step portion ST3, Fig. 12, [0110]) into the substrate (semiconductor layer 10, Fig. 12, [0113]) located laterally beyond an edge of the plurality of terminations (plurality of guard ring portions 3a to 3e, Fig. 12, [0117]); and
the contact layer (metal layer 30 is an extension of the second insulating film 22, and the portion of the second insulating film 22 on the left side of recesses is analogous to the contact layer of Sasaki in that it covers the first insulating layer and contains electrical contacts (source electrode 16 and the via contacting the source electrode) in addition to metal layer 30 as an extension, Fig. 12, [0110]) overlays the plurality of recesses (first step portion ST1, second step portion ST2, and third step portion ST3, Fig. 12).
Hiyoshi-Embodiment 1 further discloses that “by providing the plurality of step portions in this manner, the occurrence of cracking that reaches element region DR or the occurrence of serious chipping (debris) can be more reliably reduced” ([0110]), where DR is the element region corresponding the active and termination regions, and “semiconductor device 102 has further improved reliability” ([0131]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor device of Sakai to include a plurality of recesses, instead of only one recess, into the substrate located laterally beyond an edge of the plurality of terminations such that the contact layer overlays the plurality of recesses, as taught by Hiyoshi-Embodiment 1, to be able to reliably reduce the cracking or chipping reaching the active region. Thus, the combination of Sakai and Hiyoshi-Embodiment 1 meets all the limitations of claim 16.
Regarding claim 17, Sakai in view of Hiyoshi-Embodiment 1 teaches the semiconductor device of claim 16, wherein
Sakai further teaches that the first insulating layer (insulating film 15, Fig. 1) comprises a field oxide layer ([0051]: “insulating film 15 made of silicon dioxide”).
Regarding claim 18, while Sakai in view of Hiyoshi-Embodiment 1 teaches the semiconductor device of claim 16,
Sasaki does not teach that the contact layer comprises an oxynitride layer or a silicon oxynitride layer.
Hiyoshi-Embodiment 1, however, teaches a moisture resistant semiconductor device (semiconductor device 102, Fig. 12, [0130]) wherein
the contact layer (of the second insulating film 22 which is analogous to the contact layer of Sasaki in that it contains contacts (source electrode 16 and the via contacting the source electrode), Fig. 12) comprises an oxynitride layer or a silicon oxynitride layer ([0044]: “second insulating film 22 includes at least one of silicon nitride (SiN) and silicon oxynitride (SiON).”).
Hiyoshi-Embodiment 1 further teaches that silicon oxynitride (SiON) have higher moisture resistance than silicon dioxide ([0062]-[0063]), and therefore using a contact layer (second insulating film 22) made of silicon oxynitride (SiON) blocks the entry of moisture to the underlying first insulating layer ([0062]), which is silicon oxide in both Sasaki in view of Hiyoshi-Embodiment 1 and Hiyoshi-Embodiment 1. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the material of the contact layer in the semiconductor device of Sasaki in view of Hiyoshi-Embodiment 1 to be silicon oxynitride (SiON), as taught by Hiyoshi-Embodiment 1, to be able to prevent moisture to reach the first insulating layer.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) in view of Hiyoshi-Embodiment 1 (US 2016/0013137 A1, Embodiment in Fig. 12) as applied to claims 16-18 above, and further in view of Hiyoshi-Embodiment 2 (US 2016/0013137 A1, Embodiment in Fig. 16).
Regarding claim 19, while Sasaki in view of Hiyoshi-Embodiment 1 teaches the semiconductor device of claim 1,
neither Sasaki nor Hiyoshi-Embodiment 1 teaches that the second insulating layer comprises a nitride layer.
Hiyoshi-Embodiment 2, however, teaches a moisture resistant semiconductor device (semiconductor device 201, Fig. 16, [0130]), wherein the second and third insulating layers (the right portion of the second insulating layer 22 covering the recesses) is analogous to the second and third insulating layers of Sasaki in view of Hiyoshi-Embodiment 1 in terms of covering the trench, and are formed from “at least one of silicon nitride (SiN) and silicon oxynitride (SiON)” ([0044]). Therefore, Hiyoshi-Embodiment 2 teaches that the second insulating layer comprises a nitride layer.
Hiyoshi-Embodiment 2 further discloses that “by making the upper layer (second insulating film 22) of SiN and SiON having high moisture resistance the entry of moisture into element region DR can be suppressed” ([0045]), as “SiO2 has slightly low moisture resistance and has a probability of allowing moisture to permeate therethrough” ([0043]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the protecting film 1 of Sasaki in view of Hiyoshi-Embodiment 1 (see Fig. 1 of Sasaki and claim 16 rejection above) with a protective film formed from SiN and SiON, as taught by Hiyoshi-Embodiment 2, instead of SiO2 and SiN, which would further improve the moisture resistance of the semiconductor device. Thus, the combination of Sasaki, Hiyoshi-Embodiment 1, and Hiyoshi-Embodiment 2 meets the limitations of claim 19.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 2016/0163800 A1) in view of Hiyoshi-Embodiment 1 (US 2016/0013137 A1, Embodiment in Fig. 12) as applied to claims 16-18 above, and further in view of Ebihara (US 2024/0274655 A1).
Regarding claim 20, while Sasaki in view of Hiyoshi-Embodiment-1 teaches the semiconductor device of claim 16,
neither Sasaki nor Hiyoshi-Embodiment-1 teaches that the third insulating layer comprises a polyimide layer.
Ebihara, on the other hand, teaches a semiconductor device (semiconductor device, Fig 12) with a multilayer surface protection film (surface protection film 25, Fig. 12, [0093]) analogous to the multilayer surface protection film (protecting film 1) of Sasaki in view of Hiyoshi-Embodiment 1 which forms the second and third insulating layers (see claim 1 rejection above). Ebihara further teaches that organic material such as polyimide or an inorganic material such as silicon nitride can be used as the material of the surface protection film 25. Considering that the third insulating layer of Sasaki in view of Hiyoshi-Embodiment 2 is SiN ([0037]: “protecting film 1 is formed as a multilayered film. In this case, protecting film 1 is formed in contact with interlayer insulating film 71. A material forming a lower film is SiO2, for example, and a material forming an upper film formed on the lower film is SiN, for example.”), and according to the teachings of Ebihara, polyimide is a known equivalent of SiN as a protecting film. Selection of a known material for the same purpose is prima facie obvious (see MPEP 2144.06), and therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki in view of Hiyoshi-Embodiment 1 such that the third insulating layer comprises polyimide.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Saito (US 2008/0315299 A1) teaches a semiconductor device with a trench at the edge, which is relevant to all claims.
Tsubakidani (US 2023/0386953 A1) teaches a semiconductor device with a plurality of recesses at the edge, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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