Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-14, 16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Radic et al. (US Pub. No. 2009/0294843 A1), hereafter referred to as Radic.
As to claim 13, Radic discloses a semiconductor device (fig 9; [0020]), comprising:
a substrate (40) including a base section (26/27), a first active pattern (N+ source 24 on left of the gate) on the base section (26), and a second active pattern (N+ source 24 on right of the gate) on the base section (26);
a first gate structure (poly gate 60’ on left side) and a second gate structure (poly gate 60’ on the right side) between the first active pattern and the second active pattern (N+ source patterns 24); and
a gate separation layer (71/74) between the first gate structure (60’ on left) and the second gate structure (60’ on the right),
wherein the substrate (40) includes a first doping region in the first active pattern (N+ dopant in 24 on left), a second doping region in the second active pattern (N+ dopant in 24 on right), and a third doping region in the base section (N+ dopant in 27), and
wherein a level of a lowermost portion of the gate separation layer (71/74) is lower than a level of a lowermost portion of the first gate structure (poly gate 60’ on left) and a level of a lowermost portion of the second gate structure (poly gate 60’ on the right).
As to claim 14, Radic discloses the semiconductor device of claim 13 (paragraphs above),
wherein the first gate structure (60’ on left) and the second gate structure (60’ on right) are spaced apart from the first doping region (24), the second doping region (24), and the third doping region (27).
As to claim 16, Radic discloses the semiconductor device of claim 13 (paragraphs above),
wherein the gate separation layer (71) is in contact with the third doping region (27).
As to claim 18, Radic discloses the semiconductor device of claim 13 (paragraphs above),
wherein the first active pattern, the second active pattern and the base section of the substrate include impurities of a first conductivity type (P-type region 25 on left, right and lower portion), and
the first doping region, the second doping region, and the third doping region include impurities of a second conductivity type (N-type dopant in 24 on left, 24 on right and drain region 27).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radic as applied to claim 13 above, and further in view of Hoshi (US Pub. No. 2022/0069072 A1).
As to claim 15, Radic discloses the semiconductor device of claim 13 (paragraphs above).
Radic does not disclose a device isolation layer spaced apart in a first direction from the first doping region and the first gate structure,
wherein a width in the first direction of the gate separation layer is smaller than a width in the first direction of the device isolation layer.
Nonetheless, Hoshi discloses a device isolation layer spaced apart in a first direction from a first doping region and a first gate structure ([0125], fig 18).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the device isolation layer with a greater width than the gate separation layer in the structure of Radic as taught by Hoshi since this will ensure sufficient electrical separation of devices on the substrate.
Allowable Subject Matter
Claims 1-12 and 19-20 are allowed.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest all of the limitations of independent claims 1 or 19. Specifically, a second gate conductive layer between the gate separation layer and the first gate conductive layer and wherein the gate separation layer extends in a second direction to a bottom surface of the first gate dielectric layer, and wherein a level of top surface of the gate separation layer is same level as a level of a top surface of the second gate conductive layer, as recited in claim 1; and wherein each of the first gate structure and the second gate structure include a first gate dielectric layer in contact with the substrate, a first gate conductive layer on the first gate dielectric layer, a second gate dielectric layer on the first gate dielectric layer and the first gate conductive layer, and a second gate conductive layer between the gate separation layer and the first gate conductive layer, wherein a level of a lowermost portion of the gate separation layer is lower than a level of a bottom surface of the device isolation layer, as recited in claim 19. Claim 17 is objected to because the prior art fails to teach or suggest wherein a top surface of the first active pattern, a top surface of the second active pattern, a top surface of the first gate structure, and a top surface of the gate separation layer are coplanar with each other.
Dependent claims 2-12 and 20 are allowable because of their dependence from one of claims 1 or 19.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2022/0302266A1; and US Patent No. 11,715,773B2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 9/11/2026
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