Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket number: 15202-000509-US
Filling Date: 05/24/24
Priority Date: 07/31/23
Inventor: Kim et al
Examiner: Bilkis Jahan
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 1 in lines 8-9 recite “a second data storage layer between the first data storage layer and the channel layer, and a first conductive layer”. However, it is not understood from the claim language that a second data storage layer between three layers are the first data storage layer and the channel layer and a first conductive layer.
Claims 2-11 depend on claim 1. Therefore, claims 2-11 are also rejected under 112 2nd rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-12 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al (US 2017/0278859 A1, Sharang hereinafter) in view of Yoshimizu et al (US 2017/0098659 A1).
Regarding claim 1, Sharang discloses a semiconductor device (Fig. 7E), comprising: a stack structure including interlayer insulating layers 32 (Para. 42) and gate electrodes 46 (Para. 87) alternately stacked in a vertical direction; a vertical pillar 62 (Para. 132) in a hole penetrating through the stack structure 32, 46, the vertical pillar 62 including a channel layer 601, 602 (Para. 132); and protrusions 50 (Para. 122) between the vertical pillar 62 and the gate electrodes 46.
Sharang does not explicitly discloses the protrusions spaced apart from each other in the vertical direction, wherein each of the protrusions include a first data storage layer, a second data storage layer between the first data storage layer and the channel layer, and a first conductive layer, the second data storage layer includes a first side surface and a second side surface opposing each other, and the first conductive layer is in contact with the first side surface of the second data storage layer, and a material of the second data storage layer is different from a material of the first data storage layer.
However, Yoshimizu discloses the protrusions 33, 32 (Figs. 32, 45, Paras. 117, 236, 226) spaced apart from each other in the vertical direction, wherein each of the protrusions 32, 33 include a first data storage layer 35, a second data storage layer 32b between the first data storage layer 35 and the channel layer 20 (Para. 128), and a first conductive layer 70 (Para. 265), the second data storage layer 32b includes a first side surface and a second side surface opposing each other, and the first conductive layer 35 is in contact with the first side surface of the second data storage layer 32b, and a material of the second data storage layer 32b (Para. 281, SiN) is different from a material of the first data storage layer 35 (Para. 226, silicon oxide).
Yoshimizu teaches the above modification is used to store charge of the device (Para. 128). It would have been obvious to one of the ordinary skills of the art before the effective filling date of the claimed invention to substitute Sharang storage layers with Yoshimizu storage layers as suggested above to store charge of the device (Para. 128).
Regarding claim 3, Yoshimizu discloses the semiconductor device of claim 1, wherein a thickness of the second data storage layer 32 is greater than a thickness of the first data storage layer 35 in a horizontal direction perpendicular to the vertical direction (Fig. 32).
Regarding claim 4, Yoshimizu discloses the semiconductor device of claim 1, wherein each of the protrusions 32, 33 further includes a second conductive layer 70 spaced apart from the first conductive layer 70, and the second conductive layer 70 is in contact (claim does not specify directly) with the second side surface of the second data storage layer 32b.
Regarding claim 5, Yoshimizu discloses the semiconductor device of claim 1, wherein each of the protrusions further includes a first insulating layer 32a in contact with the first data storage layer 35, and the first insulating layer 32a is between the first data storage layer 35 and the second data storage layer 32b.
Regarding claim 6, Yoshimizu discloses the semiconductor device of claim 1, wherein each of the protrusions further includes an insulating layer 34 in contact with the first data storage layer 35, and wherein the first data storage layer 35 is between the insulating layer 34 and the second data storage layer 32b.
Regarding claim 7, Yoshimizu discloses the semiconductor device of claim 1, wherein each of the protrusions further includes an interfacial insulating layer 31 (Para. 117) between the second data storage layer 32b and the channel layer 20.
Regarding claim 8, Yoshimizu discloses the semiconductor device of claim 1, wherein the vertical pillar 50 (Para. 115) further includes an interfacial insulating layer 31 covering an external side surface of the channel layer 20.
Regarding claim 9, Sharang discloses the semiconductor device of claim 1, wherein the vertical pillar 62 further includes an insulating core region and a pad pattern 63 (Para. 66) on the insulating core region 62, wherein a portion of the channel layer 60 (Para. 132) is on a side surface of the insulating core region 62, and wherein the pad pattern 63 is connected to the channel layer 60.
Regarding claim 10, Sharang discloses the semiconductor device of claim 1, further comprising: a peripheral circuit structure 73 (Para. 69) vertically overlapping the stack structure 32, 46.
Regarding claim 11, Sharang discloses the semiconductor device of claim 1, wherein each of the interlayer insulating layers 32 includes a first insulating portion 153 and a second insulating portion 154 such that the interlayer insulating layers 32 provide a plurality of first insulating portions 153 and a plurality of second insulating portions 154, wherein the plurality of second insulating portions 154 are between the plurality of first insulating portions 153 and the vertical pillar 62, and wherein the protrusions 50 vertically overlap the plurality of second insulating portions 154, respectively.
Regarding claim 12, Sharang discloses a semiconductor device (Fig. 7), comprising: a stack structure 32, 46 including interlayer insulating layers 2 and gate electrodes 46 alternately stacked in a vertical direction; and a vertical structure 62 penetrating through the stack structure 32, 46, the vertical structure 62 including a vertical pillar disposed in a hole penetrating through the stack structure 32, 46, the vertical structure including protrusions 50 between the vertical pillar 62 and the gate electrodes 46, and the vertical pillar 62 including a channel layer 60.
Sharang does not explicitly disclose the protrusions are spaced apart from each other in the vertical direction, wherein the vertical structure includes a first data storage layer and a second data storage layer, wherein each of the protrusions includes at least one of the first data storage layer and the second data storage layer, wherein each of the protrusions further includes a first conductive layer in contact with at least one of the first data storage layer and the second data storage layer, and a material of the second data storage layer is different from a material of the first data storage layer.
However, Yoshimizu discloses the protrusions 32, 33 (Figures 32, 45) are spaced apart from each other in the vertical direction, wherein the vertical structure includes a first data storage layer 35 and a second data storage layer 32b, wherein each of the protrusions includes at least one of the first data storage layer 35 and the second data storage layer 32b, wherein each of the protrusions further includes a first conductive layer 70 in contact with at least one of the first data storage layer 35 and the second data storage layer 32b, and a material of the second data storage layer 32b is different from a material of the first data storage layer 35 (Paras. 226, 281).
Yoshimizu teaches the above modification is used to store charge of the device (Para. 128). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Sharang storage layers with Yoshimizu storage layers as suggested above to store charge of the device (Para. 128).
Regarding claim 14, Yoshimizu discloses the semiconductor device of claim 13, wherein each of the protrusions 32, 33 includes the first data storage layer 35, the second data storage layer 32b, and the first conductive layer 70, wherein the second data storage layer 32b is between the first data storage layer 35 and the channel layer 20, and wherein the first conductive layer 70 is in contact with the second data storage layer 32b (claim does not specify directly contact).
Regarding claim 15, Yoshimizu discloses the semiconductor device of claim 14, wherein each of the protrusions further includes a second conductive layer 70 in contact with the second data storage layer 32b, wherein the second conductive layer 70 is spaced apart from the first conductive layer 70, and wherein the second data storage layer 32 is between the first conductive layer 70 and the second conductive layer 70 (Para. 32).
Regarding claim 16, Yoshimizu discloses the semiconductor device of claim 12, wherein each of the protrusions includes the first data storage layer 35 and the first conductive layer 70, wherein the vertical pillar 50 includes the second data storage layer 32b, and wherein the second data storage layer 32b is in contact with the first conductive layer 70.
Regarding claim 17, Sharang discloses the semiconductor device of claim 12, wherein each of the interlayer insulating layers 32 includes a first insulating portion 153 (Para. 95) and a second insulating portion 154 (Para. 86), the second insulating portion 154 is between the first insulating portion 153 and the vertical pillar 62, and the protrusions 50 vertically overlap the second insulating portions 154.
Claim(s) 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al (US 2017/0278859 A1, Sharang hereinafter) in view of Yoshimizu et al (US 2017/0098659 A1) and further in view of Kim et al (US 2010/0163968 A1).
Regarding claim 18, Sharang discloses a data storage system (Fig. 7), comprising: the semiconductor device further includes a stack structure 32, 46 and a vertical structure 62 penetrating through the stack structure, the stack structure includes interlayer insulating layers 32 and gate electrodes 46 alternately stacked in a vertical direction, the vertical structure includes a vertical pillar 62 in a hole penetrating through the stack structure 32, 46, the vertical pillar 62 includes a channel layer 60, the vertical pillar 62 further includes protrusions 50 between the vertical pillar 62 and the gate electrodes 46. Sharang does not explicitly disclose the protrusions are spaced apart from each other in the vertical direction, the vertical structure includes a first data storage layer and a second data storage layer, each of the protrusions includes at least one of the first data storage layer and the second data storage layer, each of the protrusions further includes a first conductive layer in contact with at least one of the first data storage layer and the second data storage layer, and a material of the second data storage layer is different from a material of the first data storage layer.
However, Yoshimizu discloses the protrusions 32. 33 (Figs. 32, 45) are spaced apart from each other in the vertical direction, the vertical structure includes a first data storage layer 35 and a second data storage layer 32b, each of the protrusions includes at least one of the first data storage layer 35 and the second data storage layer 32b, each of the protrusions further includes a first conductive layer 70 in contact with at least one of the first data storage layer 35 (claim does not specify directly contact) and the second data storage layer 32b, and a material of the second data storage layer 32b is different from a material of the first data storage layer 35 (Pars. 226, 281).
Yoshimizu teaches the above modification is used to store charge of the device (Para. 128). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Sharang storage layers with Yoshimizu storage layers as suggested above to store charge of the device (Para. 128).
Sharang does not explicitly disclose a semiconductor device including an input/output pad; and a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device.
However, Kim discloses a semiconductor device including an input/output pad; and a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device (Fig. 16, Para. 197, I/O device considers as a pad).
Kim teaches the above modification is used to control the memory devices (Para. 195). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Sharang structure with Kim controller as suggested above to control the memory devices (Para. 195).
Regarding claim 20, Sharang discloses the semiconductor device of claim 18, wherein each of the interlayer insulating layers 32 includes a first insulating portion 153 and a second insulating portion 154, the second insulating portion 154 is between the first insulating portion 153 and the vertical pillar 62, and wherein the protrusions 50 vertically overlap the second insulating portions 154.
Claim(s) 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al (US 2017/0278859 A1, Sharang hereinafter) in view of Yoshimizu et al (US 2017/0098659 A1) and further in view of Lu et al (US 2021/0375917 A1).
Regarding claims 2 and 13, Yoshimizu discloses the first data storage layer includes a charge trap layer 33 (Para. 236).
Sharang does not explicitly disclose the second data storage layer includes a ferroelectric layer.
However, Lu discloses data storage film is a ferroelectric layer (Para. 41). Lu teaches the above modification is used to improve power efficiency of the device (Para. 42).
It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Sharang data storage film with Lu data storage film as suggested above to improve power efficiency of the device (Para. 42).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al (US 2017/0278859 A1, Sharang hereinafter) in view of Yoshimizu et al (US 2017/0098659 A1) and further in view of Kim et al (US 2010/0163968 A1) and Lu et al (US 2021/0375917 A1).
Regarding claim 19, Yoshimizu discloses the semiconductor device of claim 18, wherein the first data storage layer includes a charge trap layer 34, wherein each of the protrusions includes the first data storage layer 35, the second data storage layer 32b, and the first conductive layer 70, wherein the second data storage layer 32b is between the first data storage layer 35 and the channel layer 20, wherein the first conductive layer 20 is in contact with the second data storage layer 32b, wherein each of the protrusions further includes a second conductive layer 70 in contact (claim does not specify directly contact) with the second data storage layer 32b, wherein the second conductive layer 70 is spaced apart from the first conductive layer 70, and wherein the second data storage layer 32b is between the first conductive layer 70 and the second conductive layer 70.
Sharang does not explicitly disclose the second data storage layer includes a ferroelectric layer.
However, Lu discloses data storage film is a ferroelectric layer (Para. 41). Lu teaches the above modification is used to improve power efficiency of the device (Para. 42).
It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Sharang data storage film with Lu data storage film as suggested above to improve power efficiency of the device (Para. 42).
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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