DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 14 - 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (20210118765).
With regard to claim 14, by Kang et al. disclose a semiconductor package (for example, see fig. 1), comprising:
a lower redistribution structure (a lower redistribution structure having connection pads 122p, and a wiring 112c; for example, see paragraph [0027]) that includes lower redistribution layers (connection pads 122p, and a wiring 112c; for example, see paragraph [0027]);
a semiconductor chip structure (122) on the lower redistribution structure (the lower redistribution structure having connection pads 122p, and a wiring 112c; for example, see paragraph [0027]);
an encapsulant (131) on the semiconductor chip structure (122) and the lower redistribution structure (the lower redistribution structure having connection pads 122p, and a wiring 112c; for example, see paragraph [0027]);
an upper redistribution structure (an upper redistribution structure having redistribution vias 143V, a redistribution layer 142) that includes an upper insulating layer (141) and upper redistribution layers (142), wherein the upper insulating layer (141) is on the encapsulant (131), and the upper redistribution layers (142) are on and within the upper insulating layer (141);
a heat dissipation structure (127, 142HP, 143HV) that includes upper heat dissipation patterns (142HP) and upper heat dissipation vias (143HV), wherein the upper heat dissipation patterns (142HP) are on and within the upper insulating layer (141), and the upper heat dissipation vias (143HV) are in the upper insulating layer (141); and
a heat dissipation member (127) on the upper redistribution structure (the upper redistribution structure having redistribution vias 143V, a redistribution layer 142), wherein the heat dissipation member (127) is connected to the upper heat dissipation patterns (142HP), wherein the upper redistribution layers (142) include an uppermost upper redistribution layer (referred to as “142A1” by examiner’s annotation shown in fig. 1 below) on the upper insulating layer (141), wherein the upper heat dissipation patterns (142HP) include an uppermost upper heat dissipation pattern (referred to as “142HP1” by examiner’s annotation shown in fig. 1 below) on the upper insulating layer (131), and wherein a width (referred to as “X1” by examiner’s annotation shown in fig. 1 below) of an upper surface of the uppermost upper heat dissipation pattern (142HP1) is greater than a width (referred to as “X2” by examiner’s annotation shown in fig. 1 below) of an upper surface of the uppermost upper redistribution layer (the upper redistribution structure having redistribution vias 143V, a redistribution layer 142).
PNG
media_image1.png
538
939
media_image1.png
Greyscale
PNG
media_image2.png
569
934
media_image2.png
Greyscale
With regard to claim 15, by Kang et al. disclose an upper surface of the semiconductor chip structure (122) is not overlapped by the encapsulant (1312 as shown in fig. 1 wherein only vertical encapsulant portion in a vertical direction that is perpendicular to an upper surface of the lower redistribution structure (the lower redistribution structure having connection pads 122p, and a wiring 112c; for example, see paragraph [0027]), and wherein the upper insulating layer (131) is in contact with the upper surface of the semiconductor chip structure (122).
PNG
media_image3.png
573
922
media_image3.png
Greyscale
With regard to claim 16, by Kang et al. disclose an interconnection structure (referred to as “133A” by examiner’s annotation shown in fig. 1 below) adjacent the semiconductor chip structure, wherein the interconnection structure electrically connects the lower redistribution layers (the lower redistribution structure having connection pads 122p, and a wiring 112c; for example, see paragraph [0027]) and the upper redistribution layers (the upper redistribution structure having redistribution vias 143V, a redistribution layer 142); and an intermediate insulating layer (11a, 11b) that extends around at least a portion of the interconnection structure (133A), wherein the encapsulant (131) is on at least a portion of each of the interconnection structure (133A) and the intermediate insulating layer (11a, 11b).
PNG
media_image4.png
558
946
media_image4.png
Greyscale
With regard to claim 17, by Kang et al. disclose the semiconductor chip structure includes a semiconductor chip (121) and a conductive bonding layer (121P) on an upper surface of the semiconductor chip (121), wherein the encapsulant (both layers 131 and a bottommost insulating layer 141 can functions as the encapsulant) is on the conductive bonding layer (121P), wherein the upper heat dissipation vias (143HV) include a first upper heat dissipation via (one of vias 143HV) and a second upper heat dissipation via (one of vias 143HV), wherein the first upper heat dissipation via (one of vias 143HV) extends in the encapsulant (both layers 131 and a bottommost insulating layer 141 can functions as the encapsulant) and connects a lowermost upper heat dissipation pattern (142HP) among the upper heat dissipation patterns (142HP) and the conductive bonding layer (121P) to each other, and wherein the second upper heat dissipation via (one of vias 143HV) connects ones among the upper heat dissipation patterns (142HP) located at different distances from the lower redistribution structure (the lower redistribution structure having connection pads 122p, and a wiring 112c; for example, see paragraph [0027]).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1 - 3, and 6 - 11 are rejected under 35 U.S.C. 103 as being unpatentable over LIN et al. (20230187363) in view of Kang et al. (20210118765).
With regard to claim 1, LIN et al. disclose a semiconductor package (for example, see fig. 2), comprising:
a semiconductor chip structure (a structure having chip 1133) that includes a semiconductor chip (1133) and a conductive bonding layer (referred to as “1131A1” by examiner’s annotation shown in fig. 2 below) on an upper surface of the semiconductor chip (1133);
a lower redistribution structure (250) on a lower surface of the semiconductor chip structure (1133), wherein the lower redistribution structure (250) includes a lower insulating layer (referred to as “250A” by examiner’s annotation shown in fig. 2 below) and lower redistribution layers (referred to as “250B” by examiner’s annotation shown in fig. 2 below) in the lower insulating layer (250A);
external connection bumps (140) on a lower surface of the lower redistribution structure (250), wherein the external connection bumps (140) are electrically connected to the lower redistribution layers (250);
an encapsulant (1132) on the semiconductor chip structure (1133) and the lower redistribution structure (250);
an upper redistribution structure (130) on the semiconductor chip structure (1133), wherein the upper redistribution structure (130) includes an upper insulating layer (referred to as “130A” by examiner’s annotation shown in fig. 2 below), upper redistribution layers (referred to as “130B1” by examiner’s annotation shown in fig. 2 below) in the upper insulating layer (130A), and upper redistribution vias (referred to as “130B2” by examiner’s annotation shown in fig. 2 below) that electrically connect the upper redistribution layers (130B1) to each other;
an interconnection structure (1131) in the encapsulant (1132), wherein the interconnection structure (1131) electrically connects the lower redistribution layers (250B) and the upper redistribution layers (130B1);
a heat dissipation structure (a structure, including conductive layers 130C1 and via 130C2 as annotated in fig. 2 below, and having a metal block 101connected with the first redistribution stack layer 130; for example, see paragraph [0085], functions as a heat dissipation structure) that includes upper heat dissipation patterns (referred to as “130C1” by examiner’s annotation shown in fig. 2 below) and upper heat dissipation via (referred to as “130C2” by examiner’s annotation shown in fig. 2 below), wherein the upper heat dissipation patterns (130C1) are in the upper insulating layer (130A), and the upper heat dissipation via (130C1) connect the upper heat dissipation patterns (130C2);
an upper package (a package having devices 121, or 102) on the upper redistribution structure (130), wherein the upper package (the package having devices 121, or 102) is electrically connected to the upper redistribution layers (130); and
a heat dissipation member (a metal block 101 functions as a heat dissipation member) on at least one side of the upper package (the package having devices 121, or 102), wherein the heat dissipation member (the metal block 101 functions as the heat dissipation member) is connected to the upper heat dissipation patterns (130C1).
PNG
media_image5.png
661
1017
media_image5.png
Greyscale
LIN et al. do not clearly disclose the upper heat dissipation vias connect the conductive bonding layer.
However, Kang et al. disclose the upper heat dissipation via (referred to as “143A1” by examiner’s annotation shown in fig. 1 below; wherein the conductive vias 143A1, made of metal material (for example, see paragraph [0043]) and is connected to connective potions 132, 133 in order to dissipate the heat from the device 121, functioning as the upper heat dissipation via) connect the conductive bonding layer (the connection pad layer 121P functions as the conductive bonding layer).
PNG
media_image6.png
573
931
media_image6.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the LIN et al.’s device to have the upper heat dissipation vias connect the conductive bonding layer as taught by Kang et al. in order to enhance a high dissipation efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, LIN et al. disclose an upper surface of the conductive bonding layer (1131A) and an upper surface of the encapsulant (1132) are coplanar.
With regard to claim 3, LIN et al. disclose the conductive bonding layer (1131A) overlaps an entirety of the upper surface of the semiconductor chip (1133) in a vertical direction that is perpendicular to an upper surface of the lower redistribution structure (250).
With regard to claim 6, Kang et al. disclose a width (referred to as “X1” by examiner’s annotation shown in fig. 1 below) of each of upper surfaces of the upper heat dissipation vias (143A1) in a horizontal direction is greater than a width (referred to as “X2” by examiner’s annotation shown in fig. 1 below) of each of upper surfaces of the upper redistribution vias (143) in the horizontal direction.
PNG
media_image7.png
544
935
media_image7.png
Greyscale
PNG
media_image5.png
661
1017
media_image5.png
Greyscale
With regard to claim 7, LIN et al. disclose an upper surface of the conductive bonding layer (1131A) is in contact with the upper insulating layer (130A).
PNG
media_image7.png
544
935
media_image7.png
Greyscale
With regard to claim 8, Kang et al. disclose the upper package includes a first group of connection conductors (referred to as “142P1” by examiner’s annotation shown in fig. 1 below) and a second group of connection conductors (referred to as “142P2” by examiner’s annotation shown in fig. 1 below), wherein the first group of connection conductors (142P1) are electrically connected to the upper redistribution layers (142P, 142), and wherein the second group of connection conductors (referred to as “142P2” by examiner’s annotation shown in fig. 1 below) are connected to the upper heat dissipation patterns (referred to as “142P3” by examiner’s annotation shown in fig. 1 below; or indirectly connected to the upper heat dissipation patterns 142HP1).
PNG
media_image8.png
597
942
media_image8.png
Greyscale
With regard to claim 9, Kang et al. disclose the upper heat dissipation patterns and vias (143) each include copper and/or aluminum. (for example, see paragraph [0043]).
With regard to claim 10, Kang et al. disclose the upper heat dissipation patterns include an uppermost upper heat dissipation pattern (142HP) on the upper insulating layer (141), wherein the heat dissipation member includes a thermal interface material layer (referred to as “127A” by examiner’s annotation shown in fig. 1 below) that is in contact with the uppermost upper heat dissipation pattern (142HP), and wherein one of the heat dissipation members 127, formed in the groove, functions as a heat slug on the thermal interface material layer (127A).
PNG
media_image9.png
436
810
media_image9.png
Greyscale
With regard to claim 11, Kang et al. disclose the heat slug (127) includes aluminum, copper (for example, see paragraph [0035]).
Allowable Subject Matter
6. Claims 4, 5, 12, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4, 5, 12, 13 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the conductive bonding layer includes a titanium layer and a copper layer, wherein the titanium layer is in contact with the upper surface of the semiconductor chip, and wherein the copper layer is on the titanium layer as recited in claim 4, a width of an upper surface of the first upper heat dissipation via in a horizontal direction that is parallel with an upper surface of the lower redistribution structure is greater than a width of an upper surface of the second upper heat dissipation via in the horizontal direction as recited in claim 5, the vertical heat dissipation structure extends in the encapsulant and connects the upper heat dissipation patterns and the lower heat dissipation patterns, wherein the external connection bumps include a first group of external connection bumps and a second group of external connection bumps, wherein the first group of external connection bumps are electrically connected to the lower redistribution layers, and wherein the second group of external connection bumps are connected to the lower heat dissipation patterns as recited in claim 12.
7. Claims 18 - 20 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the second semiconductor package includes a redistribution substrate that includes a signal pattern, a power pattern, and a ground pattern; a second semiconductor chip structure on the redistribution substrate, wherein the second semiconductor chip structure is electrically connected to the signal pattern, the power pattern, and the ground pattern; a second encapsulant on the second semiconductor chip structure; and connection conductors on a lower surface of the redistribution substrate, wherein the connection conductors include a first group of connection conductors and a second group of connection conductors, the first group of connection conductors are electrically connected to at least one of the signal pattern and the power pattern, and the second group of connection conductors are electrically connected to the ground pattern, wherein the first group of connection conductors are electrically connected to the upper redistribution layers, and wherein the second group of connection conductors are connected to the heat dissipation structure as recited in claim 18.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights