DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/24/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because in figure 4 reference character “350” is indicating the solder bump instead of the protective layer.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20 recites “on the first portion” in line. This uses an incorrect preposition, the examiner suggests “[of the first portion.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 18 are is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the through pads" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner will assume that the applicant intended “the through-electrodes”
Claim 18 recites “a step difference” in line 2. It is unclear whether or not this is the same as “a step difference” recited in claim 14 line 26.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 through 6 and 10 through 12 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chen (US 2021/0375826)
Regarding claim 1.
Chen teaches:
A semiconductor package (annotated figure) comprising:
a first semiconductor chip (fig 9:102; [para 0018]) having first and second surfaces opposing each other;
first lower electrode pads (fig 9:404,410; [para 0046]) on the first surface of the first semiconductor chip (fig 9:102; [para 0018]) and electrically connected to the first semiconductor chip (fig 9:102; [para 0018]);
a first insulating layer (fig 9:402,912; [para 0044,0092]) surrounding a side surface of each of the first lower electrode pads (fig 9: 404,410; [para 0046])on the first surface of the first semiconductor chip (fig 9:102; [para 0018]);
through-electrodes (fig 9:910; [para 0099]) penetrating through at least a portion of the first semiconductor chip (fig 9:102; [para 0018]) and protruding from the second surface of the first semiconductor chip (fig 9:102; [para 0018]);
first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]) and electrically connected to the first semiconductor chip (fig 9:102; [para 0018]) through the through-electrodes (fig 9:910; [para 0099]);
a first dielectric layer (fig 9:300a; [para 0094])covering at least a portion of each of the first insulating layer (fig 9:402,912; [para 0044,0092]), the first semiconductor chip (fig 9:102; [para 0018]), the through-electrodes (fig 9:910; [para 0099]), and the first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]);
a second semiconductor chip (fig 9:202; [para 0095]) on the first dielectric layer (fig 9:300a; [para 0094]);
second electrode pads (fig 9:208b; [para 0099]) on a first surface of the second semiconductor chip (fig 9:202; [para 0095]) and electrically connected to the second semiconductor chip (fig 9:202; [para 0095]) and the first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]);
a second insulating layer (fig 9:208a; [para 0033]) surrounding side surfaces of the second electrode pads (fig 9:208b; [para 0099]) on the first surface of the second semiconductor chip (fig 9:202; [para 0095]);
a second dielectric layer (fig 9:300b; [para 0056]) covering at least a portion of each of the second semiconductor chip (fig 9:202b,202; [para 0095]) and the second insulating layer (fig 9:208a; [para 0033]);
bump structures (fig 9:420; [para 0099]) patched below the first lower electrode pads (fig 9: 404,410; [para 0046])on the first surface of the first semiconductor chip (fig 9:102; [para 0018]);
and a protective layer (fig 9:412; [para 0047]) covering at least a portion of the bump structures (fig 9:420; [para 0099]), wherein the first dielectric layer (fig 9:300a; [para 0094]) comprises a first portion (fig 9:300a2; [para 0094]) and a second portion (fig 9:300a1; [para 0094]) on the first portion (fig 9:300a2; [para 0094]) of the first dielectric layer (fig 9:300a; [para 0094]), and a first outer surface of the first portion (fig 9:300a2; [para 0094]) of the first dielectric layer (fig 9:300a; [para 0094]) is located on an inner side that is closer to the first semiconductor chip (fig 9:102; [para 0018]) than a second outer surface of the second portion (fig 9:300a1; [para 0094]) of the first dielectric layer (fig 9:300a; [para 0094]).
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Regarding claim 3.
Kim teaches the semiconductor package of claim 1, further
an outer surface of the protective layer (fig 9:412; [para 0047]) is located closer to the first semiconductor chip (fig 9:102; [para 0018]) than the first outer surface of the first portion (fig 9:300a2; [para 0094]).
Regarding claims 4.
Kim teaches the semiconductor package of claim 1, further
Kim teaches:
the first portion (fig 9:300a2; [para 0094]) surrounds at least a portion of a side surface of the first insulating layer (fig 9:402,912; [para 0044,0092]), and the second portion (fig 9:300a1; [para 0094]) surrounds at least a portion of a side surface of the first semiconductor chip (fig 9:102; [para 0018]).
Regarding claim 5.
Kim teaches the semiconductor package of claim 1, further
the protective layer (fig 9:412; [para 0047]) covers the first outer surface of the first portion (fig 9:300a2; [para 0094]), and an outer surface of the protective layer (fig 9:412; [para 0047]) is located on an inner side of the second outer surface of the second portion (fig 9:300a1; [para 0094]).
Regarding claim 6.
Kim teaches the semiconductor package of claim 1, further
Kim teaches:
the first outer surface of the first portion (fig 9:300a2; [para 0094]) is inclined in a direction away from the first semiconductor chip (fig 9:102; [para 0018]).
Regarding claim 10.
Kim teaches the semiconductor package of claim 1, further
Kim teaches:
the bump structures (fig 9:420; [para 0099]) each include a pillar portion (fig 9:422; [para 0048]) in contact with the first lower electrode pads (fig 9:404,410; [para 0046]) on the first surface of the first semiconductor chip (fig 9:102; [para 0018]) and a solder portion (fig 9:424; [para 0048]) disposed on a first surface of the pillar portion (fig 9:422; [para 0048]).
Regarding claim 11.
Kim teaches the semiconductor package of claim 1, further
Kim teaches:
the first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]) and the second electrode pads (fig 9:208b; [para 0099]) on the first surface of the second semiconductor chip (fig 9:202; [para 0095]) are in contact with each other.
Regarding claim 12.
Kim teaches the semiconductor package of claim 11, further
Kim teaches:
the first upper electrode pads (fig 9:108b; [para 0022]) on the through [electrodes] (fig 9:910; [para 0099]) and the second electrode pads (fig 9:208b; [para 0099]) on the first surface of the second semiconductor chip (fig 9:202; [para 0095]) comprise copper (Cu) ([para 0022,0033]).
Claim(s) 14, 15, 17, and 18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chen (US 2021/0375826)
Regarding claim 14.
Chen teaches:
A semiconductor package comprising:
first and second chip structures stacked in a first direction, wherein the first chip structure incudes:
a first semiconductor chip (fig 9:102; [para 0018]), first lower electrode pads (fig 9:404,410; [para 0046]) electrically connected to the first semiconductor chip (fig 9:102; [para 0018]), a first insulating layer (fig 9:402,912; [para 0044]) surrounding each of the first lower electrode pads (fig 9:404,410; [para 0046]), through-electrodes (fig 9:910; [para 0099]) penetrating through at least a portion of the first semiconductor chip (fig 9:102; [para 0018]), first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]), and a first dielectric layer (fig 9:300a; [para 0094]) covering a portion of each of the first insulating layer (fig 9:402,912; [para 0044]), the first semiconductor chip (fig 9:102; [para 0018]), the through-electrodes (fig 9:910; [para 0099]), and the first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]), wherein the second chip structure comprises:
a second semiconductor chip (fig 9:202; [para 0095]), second electrode pads (fig 9:208b; [para 0099]) electrically connected to the second semiconductor chip (fig 9:202; [para 0095]) and the first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]), a second insulating layer (fig 9:208a; [para 0033]) surrounding the second electrode pads (fig 9:208b; [para 0099]) and contacting the first dielectric layer (fig 9:300a; [para 0094]), and a second dielectric layer (fig 9:300b; [para 0056]) covering at least a portion of each of the second semiconductor chip (fig 9:202b,202; [para 0095]) and the second insulating layer (fig 9:208a; [para 0033]), wherein the first dielectric layer (fig 9:300a; [para 0094]) comprises a first portion (fig 9:300a2; [para 0094]) surrounding at least a portion of a side surface of the first insulating layer (fig 9:402,912; [para 0044]) and a second portion (fig 9:300a1; [para 0094]) surrounding a side surface of the first semiconductor chip (fig 9:102; [para 0018]), and wherein a first outer surface of the first portion (fig 9:300a2; [para 0094]) and a second outer surface of the second portion (fig 9:300a1; [para 0094]) have a step difference.
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Regarding claim 15.
Chen teaches the semiconductor package of claim 14, further
Chen teaches:
the second outer surface of the second portion (fig 9:300a1; [para 0094]) protrudes relative to the first outer surface of the first portion (fig 9:300a2; [para 0094]).
Regarding claim 17.
Chen teaches the semiconductor package of claim 14, further
Chen teaches:
bump structures (fig 9:420; [para 0099]) disposed below the first chip structure (fig 9:102; [para 0018]);
and a protective layer (fig 9:412; [para 0047]) covering at least a portion of the bump structures (fig 9:420; [para 0099]).
Regarding claim 18.
Chen teaches the semiconductor package of claim 17, further
Chen teaches:
an outer surface of the protective layer (fig 9:412; [para 0047]) has a step difference from the first outer surface and the second outer surface.
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Claim(s) 20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chen (US 2021/0375826)
Regarding claim 20.
Chen teaches:
A semiconductor package comprising:
a first semiconductor chip (fig 9:102; [para 0018]);
first lower electrode pads (fig 9:404; [para 0044]) below the first semiconductor chip (fig 9:102; [para 0018]) and electrically connected to the first semiconductor chip (fig 9:102; [para 0018]);
a first insulating layer (fig 9:402,912; [para 0044]) surrounding a side surface of each of the first lower electrode pads (fig 9:404; [para 0044]);
through-electrodes (fig 9:910; [para 0099]) penetrating through at least a portion of the first semiconductor chip (fig 9:102; [para 0018]) and protruding from an upper surface of the first semiconductor chip (fig 9:102; [para 0018]);
first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]) and electrically connected to the first semiconductor chip (fig 9:102; [para 0018]) through the through-electrodes (fig 9:910; [para 0099]);
a first dielectric layer (fig 9:300a; [para 0094]) covering a portion of each of the first insulating layer (fig 9:402,912; [para 0044]), the first semiconductor chip (fig 9:102; [para 0018]), the through-electrodes (fig 9:910; [para 0099]), and the first upper electrode pads (fig 9:108b; [para 0022]);
a second semiconductor chip (fig 9:202; [para 0095]) on the first dielectric layer (fig 9:300a; [para 0094]);
second electrode pads (fig 9:208b; [para 0099]) on a first surface of the second semiconductor chip (fig 9:202; [para 0095]) and electrically connected to the second semiconductor chip (fig 9:202; [para 0095]) and the first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]);
and a second insulating layer (fig 9:208a; [para 0033]) surrounding side surfaces of the second electrode pads (fig 9:208b; [para 0099]) on the first surface of the second semiconductor chip (fig 9:202; [para 0095]), wherein the first dielectric layer (fig 9:300a; [para 0094]) comprises a first portion (fig 9:300a2; [para 0094]) having a first width and a second portion (fig 9:300a1; [para 0094]) having a second width greater than the first width on the first portion (fig 9:300a2; [para 0094]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0375826) as applied to claim 1 and further in view of Lin (US 2013/0134559)
Regarding claim 2.
Chen teaches the semiconductor package of claim 1, above
Chen does not teach an outer surface of the protective layer is inclined.
Lin teaches:
wherein an outer surface of the protective layer (fig 9:66a; [para 0020]) is inclined so that a width of the protective layer (fig 9:66a; [para 0020]) narrows in a direction away from the first semiconductor chip (fig 9:44; [para 0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an inclined protective layer in order to provide additional protection and prevent cracking of underlying layers (paragraph 3).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0375826) as applied to claim 1 and further in view of Kim (US 2016/0027764)
Regarding claim 7.
Chen teaches the semiconductor package of claim 1, above
Chen does not teach the first dielectric layer includes a first lower dielectric layer and a first upper dielectric layer
Kim teaches:
the first dielectric layer (fig 2d:160,121; [para 0041,0069]) includes a first lower dielectric layer (fig 2d:160; [para 0069]) and a first upper dielectric layer (fig 2d:121; [para 0041]), the first lower dielectric layer (fig 2d:160; [para 0069]) surrounding a side surface of the first insulating layer (fig 2d:111; [para 0030]) and a side surface of each of the through-electrodes (fig 2d:185,180; [para 0069]), and the first upper dielectric layer (fig 2d:121; [para 0041]) surrounding a side surface of each of the upper electrode pads (fig 2d:125; [para 0043]) and contacting the second insulating layer (fig 2d:122; [para 0041]) on the first lower dielectric layer (fig 2d:160,121; [para 0041,0069]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first dielectric layer of upper and lower dielectric layers in order to accommodate stacking of different sized packages (paragraph 6)
Regarding claim 8.
Chen in view of Kim teaches the semiconductor package of claim 7, further
Kim teaches:
the first lower dielectric layer (fig 2d:160; [para 0069]) comprises the entirety of the first portion (fig 2d:161b; [para 0056]) of the first dielectric layer (fig 2d:160,121; [para 0041,0069]) and at least a portion of the second portion (fig 2d:161a; [para 0056]) of the first dielectric layer (fig 2d:160,121; [para 0041,0069]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0375826) in view of Kim (US 2016/0027764) as applied to claim 7 and further in view of Yu (US 2014/0001612)
Regarding claim 9.
Chen in view of Kim teaches the semiconductor package of claim 7, above
Kim teaches:
the first upper dielectric layer (fig 2d:121; [para 0041]) and the second insulating layer (fig 2d:122; [para 0041]) .
Chen in view of Kim does not teach the insulating material comprises at least one of silicon oxide, silicon nitride, and silicon carbonitride.
Yu teaches:
Dielectric layer (fig 12:204; [para 0019]) comprises at least one of silicon oxide, silicon nitride, and silicon carbonitride ([para 0019]).
It would have been obvious to one of ordinary skill in the art for the first upper dielectric layer and the second insulating layer comprise at least one of silicon oxide due to the dielectric properties and compatibility with semiconductor structures and manufacturing.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0375826) as applied to claim 1 and further in view of Chen (US 2021/0375826)
Regarding claim 13.
Chen teaches the semiconductor package of claim 1, above
Chen teaches:
a distance between the first outer surface of the first portion (fig 9:300a2; [para 0094]) of the first dielectric layer (fig 9:300a; [para 0094]) and the second outer surface of the second portion (fig 9:300a1; [para 0094]) of the first dielectric layer (fig 9:300a; [para 0094])
Chen does not teach the distance is 0.5 μm to 10 μm.
Chen teaches:
Forming grooves (fig 2j:g3; [para 0052]) that are 40 to 180 micron wide ([para 0052]) and then dividing the grooves with a saw 36 to 176 microns wide (fig 2j; [para 0053])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the width of the remaining groove would be 2 microns in order to use the dicing equipment from previous steps
Further, given the teaching of the references, it would have been obvious to determine the optimum widths involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0375826) as applied to claim 14 and further in view Shen (US 2012/0205800)
Regarding claim 16.
Chen teaches the semiconductor package of claim 14, above
Chen teaches:
a height of the first semiconductor chip (fig 9:102; [para 0018]) a height of the second semiconductor chip (fig 9:202; [para 0095]).
Chen does not teach a height of the first semiconductor chip is smaller than a height of the second semiconductor chip.
Shen teaches:
a height of the first semiconductor chip (fig 2k:120; [para 0045]) is smaller than a height of the second semiconductor chip (fig 2k:160; [para 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a height of the first semiconductor chip to be smaller than a height of the second semiconductor chip in order to minimize the size of the package and the length of the through substrate vias.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0375826) as applied to claim 14 and further in view Cheng (US 2018/0350784)
Regarding claim 19.
Chen teaches the semiconductor package of claim 14, above
Chen teaches:
the first upper electrode pads (fig 9:108b; [para 0022]) on the through-electrodes (fig 9:910; [para 0099]) each include a conductive layer , wherein the conductive layer comprises copper (Cu) ([para 0022]),
Chen does not teach a seed layer.
Cheng teaches:
the electrode pads (fig 17:162; [para 0035]) include a conductive layer and a seed layer covering side and lower surfaces of the conductive layer, wherein the conductive layer comprises copper (Cu), and wherein the seed layer comprises titanium (Ti) ([para 0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a titanium seed layer in order to facilitate the deposition of copper and to prevent copper contamination of underlying dielectric material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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