DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Further, “semiconductor” is misspelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 7, 10 – 18, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Croissant et al. (US 2024/0321807).
Regarding claim 1, Croissant teaches (FIG. 2):
A semiconductor device comprising:
a first substrate comprising a first layer (210);
a wall (230) coupled to a first surface of the first layer; and
a material (217) coupled to the first surface of the first layer, wherein the wall is configured to block the material from flowing outside of the wall ([0033]).
Regarding claim 2, Croissant teaches (FIG. 5B):
The semiconductor device of claim 1, wherein the wall comprises a perimeter formed using two or more layers of printed material or jetted material ([0042]), and wherein the perimeter of the wall is configured to contain the material and to block the material from flowing outside of the wall ([0033]).
Regarding claim 3, Croissant teaches (FIG. 5B):
The semiconductor device of claim 2, wherein the perimeter of the wall is at least one of circle-shaped, oval-shaped, triangle-shaped, square-shaped, or rectangular-shaped.
Regarding claim 4, Croissant teaches varying the height and width of the printed wall ([0033]):
The semiconductor device of claim 1, wherein a height of the wall is about 10 micrometers to 50 micrometers, and wherein a width of the of the wall is about 10 micrometers to 50 micrometers.
Regarding claim 5, Croissant teaches ([0034]):
The semiconductor device of claim 1, wherein the wall is formed from at least one of an oligomer, a polymer, an ink-based material, an emulsion-based material, or an inorganic material, or a combination of one or more the oligomer, the polymer, the ink-based material, the emulsion-based material, or the inorganic material into a sol, a gel, a pigment, a paste, or a solution.
Regarding claim 6, Croissant teaches (FIG. 2):
The semiconductor device of claim 1, further comprising:
a die (220) coupled to the first surface of the first layer via a connector (215);
wherein the wall is located between the first surface of the first layer and a second surface of the die (FIG. 2); and
wherein the material coupled to the first layer is located between the first surface of the first layer and the second surface of the die (FIG. 2).
Regarding claim 7, Croissant teaches varying height and width ([0033]):
The semiconductor device of claim 6, wherein a first ratio of a first height of the wall to a first width of the wall is between about 1:2 and about 1:5.
Regarding claim 10, Croissant teaches (FIG. 2, 5B):
The semiconductor device of claim 6, wherein the wall comprises a perimeter formed using two or more layers of printed material or jetted material, and wherein the perimeter of the wall is located under an edge of the die and is configured to contain the material and to block the material from flowing outside of the wall ([0033]).
Regarding claim 11, Croissant teaches varying height and width ([0033]):
The semiconductor device of claim 6, wherein a second ratio of a first height of the wall to a second height of the first substrate is between about 1:5 and about 1:2.
Regarding claim 12, Croissant teaches (FIG. 2, 5B):
The semiconductor device of claim 1, further comprising:
a second substrate (220) coupled to the first surface of the first layer via a connector (215);
wherein the wall is located between the first surface of the first layer and a second surface of the second substrate (FIG. 2); and
wherein the material coupled to the first layer is located between the first surface of the first layer and a third surface of the second substrate (FIG. 2).
Regarding claim 13, Croissant teaches (FIG. 5B):
The semiconductor device of claim 12, wherein the wall comprises a perimeter, and wherein the perimeter of the wall is configured to contain the material and to block the material from flowing outside of the wall ([0033]).
Regarding claim 14, Croissant teaches (FIG. 5B):
The semiconductor device of claim 12, wherein the wall is formed from at least one of two or more layers of a printed material or two or more layers of a jetted material ([0042]).
Regarding claim 15, Croissant teaches (FIG. 2, 5B):
A method of manufacturing one or more walls configured to block flow of material from a selected location, the method comprising:
forming a first layer of a first substrate (210);
forming a wall (230) on a first surface of the first substrate; and
coupling a material (217) to the first surface of the first substrate, wherein the wall is configured to block the material from flowing outside of the wall ([0033]).
Regarding claim 16, Croissant teaches ([0034], [0042]):
The method of claim 15, wherein the wall is formed using at least one of extrusion or jetting to form two or more layers, wherein the wall is formed from at least one of an oligomer, a polymer, or an inorganic material, or a combination of one or more the oligomer, the polymer, or the inorganic material into a sol, a gel, a pigment, a paste, or a solution.
Regarding claim 17, *** teaches:
The method of claim 15, wherein forming the first layer comprises forming an interconnect in the first layer, wherein the method further comprises:
coupling a die (220) to the first surface of the first substrate, wherein a connector (215) of the die is connected to the interconnect; and
wherein coupling a material to the first surface of the first substrate comprises inserting the material between the die and the first surface to surround the connector ([0030] – [0032]).
Regarding claim 18, Croissant teaches (FIG. 5B):
The method of claim 17, wherein the wall comprises a perimeter and wherein an internal area of the perimeter of the wall is configured to contain the material within the internal area of the perimeter of the wall ([0033]).
Regarding claim 20, Croissant teaches (FIG. 2, 5B):
A system comprising:
a first substrate comprising a first layer (210);
a wall (230) coupled to a first surface of the first layer;
a material (217) coupled to the first surface of the first layer, wherein the wall is configured to block the material from flowing outside of the wall ([0033]); and
a die (220) or a second substrate coupled to the first layer, wherein the wall and material are located between the first surface of the first layer and a second surface of the die or second substrate (FIG. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 9, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Croissant et al. (US 2024/0321807) as applied to claim 1 above, and further in view of Brun et al. (US 2024/0006312).
Regarding claim 8, Croissant teaches multiple printable materials, but fails to expressly disclose:
The semiconductor device of claim 6, wherein the wall is formed from a conductive material and is configured to be coupled to a connector of at least one of the first substrate or the die.
However, Brun teaches underfill barrier structures 108/1018 formed of conductive materials ([0034]) and placed between a substrate and a die (FIG. 9), sealed by an encapsulant material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Croissant to include conductive barrier structures as disclosed by Brun for the predictable advantage of using the barrier layer as an interconnect bus.
Regarding claim 9, Croissant teaches a stacked semiconductor package, but fails to expressly disclose:
The semiconductor device of claim 6, wherein the first substrate further comprises a second layer coupled to the first layer, and wherein the die is at least partially embedded within a second layer of the first substrate.
However, Brun teaches underfill barrier structures 108/1018 formed of conductive materials ([0034]) and placed between a substrate and a die (FIG. 9), sealed by an encapsulant material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Croissant to include the sealing encapsulant layer of Brun for the predictable advantage of improving device connection stability of the stacked package.
Regarding claim 19, Croissant teaches a stacked semiconductor package, but fails to expressly disclose:
The method of claim 18, the method further comprising: forming a second layer on the first surface of the first substrate, wherein the die, wall, and material are at least partially embedded within the second layer.
However, Brun teaches underfill barrier structures 108/1018 formed of conductive materials ([0034]) and placed between a substrate and a die (FIG. 9), sealed by an encapsulant material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Croissant to include the sealing encapsulant layer of Brun for the predictable advantage of improving device connection stability of the stacked package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
Prosecution Insights