Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species A (Claims 1-20) in the reply filed on 6/23/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the providing" in line 1. There is insufficient antecedent basis for this limitation in the claim. Additionally, it is unclear to one of skill in the art if “the bonding” recited in line 5 refers to the bonding step that is recited in claim 14 or the bonding step that is recited in claim 14. Claim 17 is indefinite because of its dependence from claim 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-11, 13-15 and 18-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bhushan et al. (US Pub. No. 2024/0421030 A1), hereafter referred to as Bhushan.
As to claim 1, Bhushan discloses a semiconductor structure (fig 2, 200; [0015]) comprising:
a logic die (fig 2, 242; [0019]);
a plurality of memory die stacks (244, 244’ [0015]) located above the logic die (242) with a plurality of gaps located between the plurality of memory die stacks (gaps between 244 and 244’; [0019]); and
a high thermal conductive material (220; [0029]) located within the plurality of gaps (gaps between 244 and 244’).
As to claim 2, Bhushan discloses the semiconductor structure of claim 1 (paragraphs above),
a redistribution layer (fig 2, layer including 222/226) located atop the logic die (242) and between the logic die (242) and the plurality of memory die stacks (244, 244’).
As to claim 3, Bhushan discloses the semiconductor structure of claim 2 (paragraphs above),
wherein the RDL (222/226) includes a dielectric material (222; [0016]).
As to claim 4, Bhushan discloses the semiconductor structure of claim 2 (paragraphs above),
wherein the RDL (222/226) includes a material selected from a group consisting of diamond, aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, copper, and a composite of dielectric material and metal ([0016]).
As to claim 5, Bhushan discloses the semiconductor structure of claim 1 (paragraphs above),
a heat spreader (208) located above the plurality of memory die stacks (244, 244’) and in contact with the high thermal conductive material (220) located within the plurality of gaps (between 244, 244’).
As to claim 7, Bhushan discloses the semiconductor structure of claim 1 (paragraphs above),
wherein the high thermal conductive material (220) within the plurality of gaps surrounds sides of at least one of the plurality of memory die stacks (244, 244’).
As to claim 8, Bhushan discloses a semiconductor structure (fig 2, 200; [0015]) comprising:
a logic die (242) including a redistribution layer (222/226);
a plurality of memory die stacks (244, 244’) located on the RDL (222/226) with a plurality of gaps located between the plurality of memory die stacks (gaps between 244 and 244’); and
a high thermal conductive material (220) located within the plurality of gaps (gaps between 244 and 244’).
As to claim 9, Bhushan discloses the semiconductor structure of claim 8 (paragraphs above),
wherein the RDL includes a dielectric material ([0016]).
As to claim 10, Bhushan discloses the semiconductor structure of claim 8 (paragraphs above),
wherein the RDL includes a material selected from a group consisting of diamond, aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, copper, and a composite of dielectric material and metal ([0016]).
As to claim 11, Bhushan discloses the semiconductor structure of claim 8 (paragraphs above),
a heat spreader (208) located above the plurality of memory die stacks (244, 244’) and in contact with the high thermal conductive material (220) located within the plurality of gaps (between 244 and 244’).
As to claim 13, Bhushan discloses the semiconductor structure of claim 8 (paragraphs above),
wherein the high thermal conductive material (220) within the plurality of gaps surrounds sides of at least one of the plurality of memory die stacks (244, 244’).
As to claim 14, Bhushan discloses a method of forming a semiconductor structure (figs 3-9B; [0006]), the method comprising:
providing a logic die (242) prepared with a redistribution layer (222/226);
bonding a plurality of memory die stacks (244, 244’) to the RDL (222/226); and
providing a high thermal conductive material (220) within a plurality of gaps located between the plurality of memory die stacks (244 and 244’), wherein the high thermal conductive material (220) is in contact with the RDL (222).
As to claim 15, Bhushan discloses the method of claim 14 (paragraphs above),
providing a heat spreader (208) on top of the plurality of memory die stacks (244, 244’) and in contact with the high thermal conductive material (220) within the plurality of gaps (gaps between 244, 244’).
As to claim 18, Bhushan discloses the method of claim 14 (paragraphs above),
wherein the RDL includes a dielectric material ([0016]).
As to claim 19, Bhushan discloses the method of claim 14 (paragraphs above),
wherein the RDL includes a material selected from a group consisting of diamond, aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, copper, and a composite of dielectric material and metal ([0016]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6, 12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhushan in view of Sun et al. (US Pub. No. 2023/0361068 A1), hereafter referred to as Sun.
As to claim 6, Bhushan discloses the semiconductor structure of claim 1 (paragraphs above).
Bhushan does not disclose wherein the high thermal conductive material is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal.
Nonetheless, Sun discloses wherein a high thermal conductive material is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal (fig 10, gap fill materials 100, 102, 92; [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the high thermal conductive material of Bhushan from a material as taught by Sun since this will improve thermal dissipation.
As to claim 12, Bhushan discloses the semiconductor structure of claim (paragraphs above).
Bhushan does not disclose wherein the high thermal conductive is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal.
Nonetheless, Sun discloses wherein a high thermal conductive material is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal (fig 10, gap fill materials 100, 102, 92; [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the high thermal conductive material of Bhushan from a material as taught by Sun since this will improve thermal dissipation.
As to claim 20, Bhushan discloses the method of claim 14 (paragraphs above).
Bhushan does not disclose wherein the high thermal conductive material located within the plurality of gaps is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal.
Nonetheless, Sun discloses wherein a high thermal conductive material is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal (fig 10, gap fill materials 100, 102, 92; [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the high thermal conductive material of Bhushan from a material as taught by Sun since this will improve thermal dissipation.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhushan in view of Chen et al. (US Pub. No. 2020/0365593 A1), hereafter referred to as Chen.
As to claim 16, Bhushan discloses the method of claim 14 (paragraphs above),
wherein the providing the plurality of memory die stacks (244, 244’) includes:
providing a plurality of memory wafers ([0015]);
bonding the plurality of memory wafers ([0015]); and
after the bonding, singulating the plurality of gaps in the plurality of memory wafers to form the plurality of memory die stacks ([0015]).
Bhushan does not disclose that the singulating is performed by etching.
Nonetheless, Chen discloses wherein singulating a plurality of dies is performed by etching ([0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to perform the singulating of the wafers of Bhushan using an etching process as taught by Chen since this will improve the manufacturing speed by simultaneously cutting the die streets.
As to claim 17, Bhushan in view of Chen disclose the method of claim 16 (paragraphs above).
Chen further discloses wherein the etching is selected from a group consisting of wet etching, dry etching and a combination of both ([0056]).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20210375827 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 7/28/2026
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