DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/07/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the isolation layer (claims 1, 10, and dependents) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 13 recites the limitation "the passivation layer" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, claim 13 will be read as “further comprising one or more redistribution layers on the silicon wafer.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9, 11, 17, 18, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bouvier et al. (Enabling Technologies for Advanced Wafer Level Camera Integration, IEEE; herein known as Bouvier).
Regarding claim 9, Bouvier teaches (annotated Fig. below) a glassless wafer-level optical sensor package comprising: a silicon wafer (Sub); an optical sensor (OS) disposed on the silicon wafer; a dam (Dam) supported on the silicon wafer and at least partially surrounding the optical sensor; and circuitry (Cir) attached to the optical sensor formed using a through-silicon via process (p. 1346, Cavity first) on the wafer.
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Regarding claim 11, Bouvier teaches the glassless wafer-level optical sensor package of claim 9, wherein the dam is formed on the silicon wafer by photo-masked epoxy (p. 1348, Spacer geometry results).
Regarding claim 17, Bouvier teaches (annotated Fig. 3 below) a system for producing a glassless wafer-level optical sensor package comprising (p. 1346, Cavity first): a glass carrier substrate (CW); a silicon wafer (Sub) supported on the glass carrier substrate; an optical sensor (OS) disposed on the silicon wafer and facing the glass carrier substrate; and a dam (Dam) formed on the silicon wafer and supporting the silicon wafer above the glass carrier substrate, wherein the dam substantially surrounds the optical sensor (see annotated Fig. 3 below, p. 1346, Cavity first).
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Regarding claim 18, Bouvier teaches (annotated Fig. 3 above) the system of claim 17, further comprising: a through-silicon via process (p. 1346, Cavity first) for connecting circuitry (Cir) to the optical sensor (OS).
Regarding claim 19, Bouvier teaches the system of claim 17, wherein the dam is formed using photo-masked epoxy (p. 1348, Spacer geometry results).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Bouvier in view of Oh (US PGPub 2023/0129129; herein known as Oh).
Regarding claim 1, Bouvier teaches (annotated Fig. 3 below) a method of manufacturing a glassless wafer-level optical sensor package comprising: forming one or more dams (S1, Dam) at least partially surrounding one or more optical sensors (OS) on a wafer (Sub); supporting the wafer on a carrier substrate (CW) via the one or more dams (Dam); forming a wafer-level optical sensor integrated circuit (Cir) for each of the one or more optical sensors on the wafer by: performing a through-silicon via process (p. 1346, Cavity first) on the wafer; removing the wafer from the carrier substrate (S3).
Bouvier does not explicitly teach: forming an isolation layer on the wafer, and performing a passivation operation on the wafer, and singulating each wafer-level optical sensor integrated circuit.
In analogous art, Oh teaches forming an isolation layer (160, [0051]) on the wafer and performing a passivation operation ([0051]) on the wafer and singulating each wafer-level optical sensor integrated circuit ([0102]). It is interpreted that the passivation operation consists application of an isolation layer, absent further specification of the process step in the specification or figures of the instant application.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier and of Oh to include forming an isolation layer on the wafer, and performing a passivation operation on the wafer, and singulating each wafer-level optical sensor integrated circuit in order to cover and protect underlying materials (Oh, [0051]) and additionally in order to utilize individual die for their intended use.
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Regarding claim 2, Bouvier in view of Oh teaches the method of claim 1, wherein forming the one or more dams at least partially surrounding the one or more optical sensors on the wafer comprises: forming the one or more dams using photo-masked epoxy (p. 1348, Spacer geometry results).
Regarding claim 4, Bouvier in view of Oh teaches the method of claim 1, wherein the carrier substrate comprises a glass carrier substrate, but not explicitly teach wherein the glass carrier substrate is configured to enable testing of the one or more optical sensors using light received at the one or more optical sensors through the glass carrier substrate, however the structure of Bouvier in view of Oh is equivalent to the structure of the device of the instant application, and therefore would necessarily be capable of enabling testing of the one or more optical sensors using light received at the one or more optical sensors through the glass carrier substrate.
Regarding claim 5, Bouvier in view of Oh teaches the method of claim 1, but does not explicitly teach wherein forming the wafer-level optical sensor integrated circuit from the wafer further comprises: forming at least one redistribution layer on the wafer.
In analogous art, Oh further teaches forming at least one redistribution layer (150, [0047]) on the wafer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier and Oh to include forming at least one redistribution layer on the wafer in order to provide connection from the substrate to an external board of an electronic device (Oh, [0052]).
Regarding claim 6, Bouvier in view of Oh teaches the method of claim 1, wherein forming the wafer-level optical sensor integrated circuit from the wafer further comprises: performing a silicon thinning operation on the wafer before performing the through-silicon via process on the wafer (p. 1348, Spacer geometry results).
Regarding claim 7, Bouvier in view of Oh teaches the method of claim 1, wherein forming the wafer-level optical sensor integrated circuit from the wafer further comprises: attaching one or more solder balls to one or more signal pads of the wafer-level optical sensor integrated circuit (S3, see annotated Fig. 3).
Regarding claim 8, Bouvier in view of Oh teaches the method of claim 1, wherein singulating each wafer-level optical sensor integrated circuit comprises separating a first wafer-level optical sensor integrated circuit from a second wafer-level optical sensor integrated circuit using a mechanical saw (Oh, [0102]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Bouvier in view of Oh as applied to claim 2 above, and further in view of Lin et al. (US PGPub 2021/0225914; herein known as Lin).
Regarding claim 3, Bouvier in view of Oh teaches the method of claim 2, wherein forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer.
Bouvier in view of Oh does not explicitly teach forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer.
In analogous art, Lin teaches forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer ([0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier in view of Oh and of Lin to include forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer in order to reduce or eliminate incident light toward the light sensing area of the image sensor (Lin, [0032]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bouvier as applied to claim 9 above, and further in view of Chen et al. (US PGPub 2020/0098811; herein known as Chen).
Regarding claim 10, Bouvier teaches the glassless wafer-level optical sensor package of claim 9, but does not explicitly teach an isolation layer on the wafer opposite the optical sensor; and a passivation layer over the isolation layer.
In analogous art, Chen teaches an isolation layer (110, [0020]) on the wafer opposite the optical sensor; and a passivation layer (110, not shown for simplicity, [0020]) over the isolation layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier and of Chen to include an isolation layer on the wafer opposite the optical sensor; and a passivation layer over the isolation layer in order to provide protection to the backside of the package device (Chen, [0032]).
Claims 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bouvier as applied to claims 9 and 17 above, and further in view of Lin.
Regarding claim 12, Bouvier teaches the glassless wafer-level optical sensor package of claim 11, but does not explicitly teach wherein the dam is formed to a height of between 30 microns and 60 microns above a surface of the wafer.
In analogous art, Lin teaches forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer ([0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier in view of Oh and of Lin to include forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer in order to reduce or eliminate incident light toward the light sensing area of the image sensor (Lin, [0032]).
Regarding claim 20, Bouvier teaches the system of claim 17, but does not explicitly teach herein the dam is of a height between 30 microns and 60 microns above a surface of the silicon wafer.
In analogous art, Lin teaches forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer ([0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier in view of Oh and of Lin to include forming the one or more dams to a height of between 30 microns and 60 microns above a surface of the wafer in order to reduce or eliminate incident light toward the light sensing area of the image sensor (Lin, [0032]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Bouvier as applied to claim 9 above, and further in view of Oh.
Regarding claim 13, Bouvier teaches the glassless wafer-level optical sensor package of claim 9, but does not explicitly teach further comprising one or more redistribution layers on the passivation layer.
In analogous art, Oh further teaches at least one redistribution layer (150, [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier and Oh to include forming at least one redistribution layer on the wafer in order to provide connection from the substrate to an external board of an electronic device (Oh, [0052]).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bouvier as applied to claim 9 above.
Regarding claim 14, Bouvier teaches the glassless wafer-level optical sensor package of claim 9, but does not explicitly teach wherein an overall thickness of the glassless wafer-level optical sensor package is between about 120 and 180 microns.
The specification of the instant application fails to teach criticality or an unexpected result of the claimed range of thickness of the glassless wafer-level optical sensor package between about 120 and 180 microns, only teaching that a thinner package is desirable to enable smaller, thinner device size ([0057]). The instant application further teaches wherein the overall thickness of the package is a result of design choices of wafer thickness and a glassless structure.
Bouvier teaches that a glassless structure results in a desirably thinner package, and additionally teaches wherein the thickness of the underlying silicon substrate of the package can be thinned to a desired thickness, in order to balance thinness of the overall package with wafer warpage concerns (p. 1347, Wafer level spacer for optics). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an overall thickness of the glassless wafer-level optical sensor package is between about 120 and 180 microns as a result-effective variable of wafer grinding, in order to achieve a suitably thin package without detrimental wafer warpage effects. See MPEP 2144.05.II(B).
Regarding claim 15, Bouvier teaches the glassless wafer-level optical sensor package of claim 9, but does not explicitly teach wherein an overall thickness of the glassless wafer-level optical sensor package is less than 200 microns.
The specification of the instant application fails to teach criticality or an unexpected result of the claimed range of thickness of the glassless wafer-level optical sensor package is less than 200 microns, only teaching that a thinner package is desirable to enable smaller, thinner device size ([0057]). The instant application further teaches wherein the overall thickness of the package is a result of design choices of wafer thickness and a glassless structure.
Bouvier teaches that a glassless structure results in a desirably thinner package, and additionally teaches wherein the thickness of the underlying silicon substrate of the package can be thinned to a desired thickness, in order to balance thinness of the overall package with wafer warpage concerns (p. 1347, Wafer level spacer for optics). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an overall thickness of the glassless wafer-level optical sensor package is less than 200 microns as a result-effective variable of wafer grinding, in order to achieve a suitably thin package without detrimental wafer warpage effects. See MPEP 2144.05.II(B).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Bouvier as applied to claim 9 above, further in view of Lim et al. (US PGPub 2019/0229139; herein known as Lim).
Regarding claim 16, Bouvier teaches the glassless wafer-level optical sensor package of claim 9, but does not explicitly teach wherein the glassless wafer-level optical sensor package comprises a fan-in wafer-level package.
In analogous art, Lim teaches a fan-in wafer-level package ([0066]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bouvier and of Lim to include a fan-in wafer-level package in order to improve electrical characteristics and reduce manufacturing cost (Lim, [0066]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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