Prosecution Insights
Last updated: October 27, 2026
Application No. 18/674,263

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Non-Final OA §102§112
Filed
May 24, 2024
Priority
Nov 22, 2023 — RE 10-2023-0162850
Examiner
KIELIN, ERIK J
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
73%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
439 granted / 648 resolved
+7.7% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
33 currently pending
Career history
685
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.7%
+6.7% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
25.4%
-14.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 648 resolved cases

Office Action

§102 §112
DETAILED ACTION Table of Contents I. Notice of Pre-AIA or AIA Status 3 II. Election/Restrictions 3 III. Drawings 3 IV. Claim Objections 5 V. Claim Rejections - 35 USC § 112 5 A. Claims 1-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 5 1. Claim 1 5 2. Claim 8 6 3. Claim 15 7 4. Claim 17 7 VI. Claim Rejections - 35 USC § 102 8 A. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0318968 (“Seo”). 8 VIII. Allowable Subject Matter 10 VI. Pertinent Prior Art 13 Conclusion 14 [The rest of this page is intentionally left blank.] I. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . II. Election/Restrictions Applicant’s election without traverse of invention group I, species group A, claims 1-17, in the reply filed on 08/18/2026 is acknowledged. III. Drawings (1) The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “174” has been used to designate both an unknown part of the meta lines M3a as well as a part of the dielectric material formed between the metal lines. (2) The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an intersection point of the third side surface and the fourth side surface forms an inflection point” of the first and second subpatterns, as recited in claim 8, must be shown or the feature(s) canceled from the claim(s). In this regard, as best as understood by Examiner as to what constitutes a subpattern, none of the claimed subpatterns show an inflection point. By definition, an inflection point defines a change in the direction of the curvature, e.g. from concave to convex or convex to concave. Note that each of the terms “subpattern” and “inflection point” are only recited in the claims, the former term only regurgitated in the Summary and neither term is used in the context of the discussion of the drawings. Moreover, the claimed third and fourth subpatterns appear to equate only to the ends of the sub-lines, M3a and M3b, while the first and second subpatterns equate to the ends of lines, M2a and M2b—to which claim 8 is directed—as consistent with the Instant Specification at, e.g. paragraph [0045]. Fig. 2A shows that the curvature of each of the ends of lines M2a and M2b is convex without an inflection point. No new matter should be entered. (3) Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. IV. Claim Objections Claim 8 is objected to because of the following informalities: In line 3 of claim 8, replace “awidth” with “a width” to correct typographical error. Appropriate correction is required. V. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. A. Claims 1-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 1. Claim 1 Claim 1 reads in pertinent part, [4] wherein at least one of the first interconnection lines comprises a first subpattern and a second subpattern overlapping in the first direction and spaced apart from each other, [5] wherein at least one of the second interconnection lines comprises a third subpattern and a fourth subpattern overlapping in the first direction and spaced apart from each other, [6] wherein two ends of the first subpattern and the second subpattern facing each other in the first direction have a convex protruding shape, and [7] wherein two ends of the third subpattern and the fourth subpattern facing each other in the first direction have a concave protruding shape. First, with regard to feature [6], it is unclear if the “two ends” pertain to one end each of each of the first and second subpatterns, or to two ends each of each of the first and second subpatterns. Second, features [4] and [6] requires a single interconnection line to have first and second, spaced-apart, overlapping subpatterns, whose subpattern ends face each other. The ends of a single line extending in a single direction, cannot face each other, as they necessarily face away from each other. As shown in the figures, the interconnection lines, e.g. M2a, M2b in Fig. 2A, are two separate lines, not one line. In other words, even a single line cut into two lines, is no longer a line. As such, the first and second subpatterns pertain to two separate lines rather than to a single line. The same lack of clarity applies to features [5] and [7]. The lack of clarity is further exacerbated by the fact that the language of the claims, e.g. “subpattern” and “two ends”, are used nowhere in the specification in the discussion of any of the specific drawings. Claims 2-14 are rejected for including the same indefinite feature by depending from claim 1. 2. Claim 8 Claim 8 recites the limitations “a first side surface”, “a second side surface”, “a third side surface”, “a fourth side surface”, “the third side surface”, and “the fourth side surface”. There is unclear antecedent basis for these limitations in the claim. In this regard, the first through fourth side surfaces recited in claim 8 pertain to the first subpattern and second subpattern. Claim 8 depends from claim 5, claim 5 pertaining to the third subpattern and fourth subpattern. Claim 5 already recites each of “a first side surface”, “a second side surface”, “a third side surface”, “a fourth side surface”, “the third side surface”, and “the fourth side surface”. Consequently, it is unclear if the recitation in claim 9 of each of “a first side surface”, “a second side surface”, “a third side surface”, “a fourth side surface”, “the third side surface”, and “the fourth side surface” pertains to the third and fourth subpatterns in claim 5 or to the first and second subpatterns recited in claim 8. Claims 9 and 10 are rejected for including the same indefinite feature by depending from claim 8, either directly or indirectly. 3. Claim 15 [3a] first subpatterns and second subpatterns, overlapping in the first direction between the plurality of spacers, on the lower structure, [3b] the first subpatterns and second subpatterns having two ends opposite to each other being spaced apart from each other and protruding convexly; [4a] third subpatterns and fourth subpatterns spaced apart from the first subpatterns and the second subpatterns in the second direction, between the plurality of spacers, on the lower structure, and overlapping in the first direction, [4b] the third subpatterns and the fourth subpatterns having two ends opposite to each other being spaced apart from each other and protruding concavely; With regard to feature [3b], it is unclear if the “two ends” pertain to one end each of each of the first and second subpatterns, or to two ends each of each of the first and second subpatterns. The same lack of clarity applies to feature [4b]. 4. Claim 17 Claim 17 reads, 17. The semiconductor device of claim 15, further comprising: [1] first protrusions on a portion of an upper surface of the first cut spacer and on sides of the first cut spacer; and [2] second protrusions on a portion of an upper surface of the second cut spacer and on sides of the second cut spacer, [3] wherein an upper surface of the first protrusions and an upper surface of the second protrusions are coplanar with the upper surface of the first cut spacer and the upper surface of the second cut spacer. As drafted, it is unclear as to what structure the first and second protrusions pertain, the claimed cut spacer or to one of the subpatterns or to something else. The specification indicates protrusions 174 and 176 are on the cut spacers. The reference characters 174 in Fig. 2A points to both a portion of a metal line and to the dielectric material making up the cut spacer CS1 and the reference characters 176 in Fig. 2B points only to a portion of metal lines. For the purposes of examination, the claims will be interpreted as best understood in light of the drawings. VI. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. A. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0318968 (“Seo”). With regard to claim 1, Seo discloses, generally in Figs. 20, 21A, and 21B, 1. A semiconductor device comprising: [1] a lower structure 100; [2] a dielectric layer IL on the lower structure 100; and [3] first interconnection lines [some of conductive patterns CP in Fig. 20] and second interconnection lines [others of CP in Fig. 20] extending in a first direction D2 in the dielectric layer IL and alternately disposed and spaced apart from each other in a second direction D1, perpendicular to the first direction D2, [4] wherein at least one of the first interconnection lines CP1 or CP2 comprises a first subpattern and a second subpattern overlapping in the first direction D2 and spaced apart from each other [see annotated Fig. 20 below], [5] wherein at least one of the second interconnection lines CP2 and CP3 comprises a third subpattern [generally at SW3] and a fourth subpattern [generally at SW4] overlapping in the first direction D2 and spaced apart from each other [see annotated Fig. 20 below], [6] wherein two ends of the first subpattern and the second subpattern facing each other in the first direction have a convex protruding shape [as shown in annotated Fig. 20 below], and [7] wherein two ends of the third subpattern and the fourth subpattern facing each other in the first direction have a concave protruding shape [as shown in annotated Fig. 20 below]. With regard to claims 2 and 3, Seo further discloses, 2. The semiconductor device of claim 1, further comprising: [1] a first cut spacer comprising the dielectric layer IL between the first subpattern and the second subpattern; and [2] a second cut spacer comprising the dielectric layer IL between the third subpattern and the fourth subpattern. 3. The semiconductor device of claim 2, wherein the first cut spacer and the second cut spacer have different shapes [as shown in Fig. 20]. As consistent with the Instant Application, the first and second cut spacers are the portions of the dielectric layer IL formed between the first and second subpatterns and between the third and fourth subpatterns, respectively, shown in Figs. 20, 21A, and 21B. VIII. Allowable Subject Matter Pending overcoming the rejection under 35 USC 112(b), above, claims 4-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 4 reads, 4. The semiconductor device of claim 1, wherein a separation distance between the third subpattern and the fourth subpattern decreases toward a center line of a width of the third subpattern and the fourth subpattern. The limitations of this claim are shown in, but not limited by, Fig. 2B. The prior art does not reasonably teach or suggest—in the context of claim 4—the limitations recited in claim 4. Claims 5-10 are allowed at least for including the same allowable limitations by depending from claim 4, either directly or indirectly. Claim 11 reads, 11. The semiconductor device of claim 1, wherein a separation distance between the first subpattern and the second subpattern is less than twice a separation distance between the first interconnection lines and the second interconnection lines. The prior art does not reasonably teach or suggest—in the context of claim 11—the limitations recited in claim 11 because the separation distances between the facing subpatterns are not discussed or otherwise clarified in Seo. Claim 12 reads, 12. The semiconductor device of claim 2, further comprising: [1] first protrusions protruding from adjacent second interconnection lines on two sides of the first cut spacer and on the dielectric layer of the first cut spacer; and [2] second protrusions protruding from adjacent first interconnection lines on two sides of the second cut spacer and on the dielectric layer of the second cut spacer. While Fig. 20 of Seo discloses the limitations of feature [1] of claim 12, Seo does not disclose the limitations of feature [2], which is not reasonably taught or suggested—in the context of claim 12. Claims 13 and 14 are allowed at least for including the same allowable limitations by depending from claim 12 either directly or indirectly. Pending overcoming the rejection under 35 USC 112(b), above, claims 15-17 would be allowed. The following is a statement of reasons for the indication of allowable subject matter: Claim 15 reads, 15. A semiconductor device comprising: [1] a lower structure; [2] a plurality of spacers extending in a first direction on the lower structure and spaced apart in a second direction perpendicular to the first direction; [3a] first subpatterns and second subpatterns, overlapping in the first direction between the plurality of spacers, on the lower structure, [3b] the first subpatterns and second subpatterns having two ends opposite to each other being spaced apart from each other and protruding convexly; [4a] third subpatterns and fourth subpatterns spaced apart from the first subpatterns and the second subpatterns in the second direction, between the plurality of spacers, on the lower structure, and overlapping in the first direction, [4b] the third subpatterns and the fourth subpatterns having two ends opposite to each other being spaced apart from each other and protruding concavely; [5a] a first cut spacer between the first subpattern and the second subpattern, [5b] a material of the first cut spacer being same as a material of the plurality of spacers; and [6a] a second cut spacer between the third subpattern and the fourth subpattern, [6b] a material of the second cut spacer being same as the material of the plurality of spacers, [7] wherein a minimum separation distance between the first subpattern and the second subpattern is less than a minimum separation distance between the third subpattern and the fourth subpattern. With regard to claim 15, Seo discloses, generally in Figs. 20, 21A, and 21B, 15. A semiconductor device comprising: [1] a lower structure 100; [2] a plurality of spacers [as consistent with the Instant Application, the portions of the dielectric layer IL between adjacent conductive patterns CP extending in the D2 direction] extending in a first direction D2 on the lower structure 100 and spaced apart in a second direction D1 perpendicular to the first direction D2; [3a] first subpatterns and second subpatterns [some of the CP in Fig. 20], overlapping in the first direction D2 between the plurality of spacers, on the lower structure 100, [3b] the first subpatterns and second subpatterns having two ends opposite to each other being spaced apart from each other and protruding convexly [as shown in annotated Fig. 20 above]; [4a] third subpatterns and fourth subpatterns [other of the CP in Fig. 20] spaced apart from the first subpatterns and the second subpatterns in the second direction D1, between the plurality of spacers, on the lower structure, and overlapping in the first direction, [4b] the third subpatterns and the fourth subpatterns having two ends opposite to each other being spaced apart from each other and protruding concavely [as shown in annotated Fig. 20 above]; [5a] a first cut spacer between the first subpattern and the second subpattern [i.e. the first cut spacer is the portion of the dielectric layer IL between the ends of the first and second subpatterns, as shown in annotated Fig. 20, above], [5b] a material of the first cut spacer being same as a material of the plurality of spacers [i.e. the dielectric IL]; and [6a] a second cut spacer between the third subpattern and the fourth subpattern [i.e. the second cut spacer is the portion of the dielectric layer IL between the ends of the third and fourth subpatterns, as shown in annotated Fig. 20, above], [6b] a material of the second cut spacer being same as the material of the plurality of spacers [i.e. the dielectric IL], [7] … [not taught] … With regard to feature [7] of claim 15, [7] wherein a minimum separation distance between the first subpattern and the second subpattern is less than a minimum separation distance between the third subpattern and the fourth subpattern. Seo does not disclose the limitations recited in feature [7], which is not reasonably taught or suggested—in the context of the claim 15. Claims 16 and 17 would be allowed at least for including the same allowable limitations by depending from claim 15. VI. Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2023/0075390 (“Son”) is cited for Fig. 22 which is similar to Fig. 1 of the Instant Application. US 2015/0147882 (“Yao”) is cited for Figs. 16A which is similar to Fig. 2B of the Instant Application. Each of the following references is cited for disclosing all of the limitations of at least claim 1: US 2017/0243818 (“Aburada”): See at least Figs. 11, 12, and 13B and the associated text. US 2022/0375962 (“Jeong”): See at least Figs. 13 and 27 and the associated text. US 2023/0005838 (“Choi”): See at least Figs. 1 and 3 and the associated text. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Signed, /ERIK KIELIN/ Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

May 24, 2024
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
73%
With Interview (+5.6%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 648 resolved cases by this examiner. Grant probability derived from career allowance rate.

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