Prosecution Insights
Last updated: October 27, 2026

Erik J Kielin, USPTO Patent Examiner

Listed by the USPTO as KIELIN, ERIK J

Tech Center 2800 • Art Units: 2814 2815 2893

This examiner grants 68% of resolved cases

Analysis

This examiner is assigned to Tech Center 2800 and Art Unit 2814, with 648 resolved cases. The allowance rate is 67.7%, and the median time to allowance is 868 days. The record supports a meaningful view of prosecution behavior, with an allowance outcome below profiles characterized by very high allowance rates and a median timeline that remains important for filing strategy.

The interview lift is 5.6%, indicating a limited positive association between interviews and allowance outcomes. Interviews may still help clarify technical or claim issues, but the data does not suggest relying on them as the primary lever. The leading companies are Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and KIOXIA Corporation. The leading firms are FISH & RICHARDSON P.C., BIRCH STEWART KOLASCH & BIRCH, and CANTOR COLBURN LLP.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

67.7%
Allow Rate
At TC average
685
Total Applications
+5.6%
Interview Lift
868
Avg Prosecution Days
Based on 648 resolved cases, 2023–2026

Rejection Statute Breakdown

0.1%
§101 Eligibility
25.0%
§102 Novelty
46.7%
§103 Obviousness
25.4%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18767435 CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME Non-Final OA Samsung Electronics Co., Ltd.
18674263 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Non-Final OA Samsung Electronics Co., Ltd.
18429611 INTEGRATED CIRCUIT DEVICES Final Rejection SAMSUNG ELECTRONICS CO., LTD.
18397231 ORGANIC LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME Non-Final OA Samsung Electronics Co., Ltd.
18753757 DISPLAY DEVICE Non-Final OA Samsung Display Co., LTD.
18442336 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME Non-Final OA Toshiba Electronic Devices & Storage Corporation
18719575 SILICON CARBIDE SUBSTRATE, METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE Non-Final OA DENSO CORPORATION
18713288 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Non-Final OA SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
18740673 COATING PROCESSING APPARATUS AND METHOD FOR FORMING COATING FILM Non-Final OA Kioxia Corporation
18605999 MEMORY DEVICE Final Rejection Kioxia Corporation
18066206 Integrated circuit FLUID sensor Non-Final OA Texas Instruments Incorporated
18667255 EMBEDDED COOLING FOR AN INTEGRATED CIRCUIT CONFIGURED WITH A BACKSIDE POWER RAIL Final Rejection NVIDIA CORPORATION
18244175 SEMICONDUCTOR POWER MODULE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR POWER MODULE FOR A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Non-Final OA Hitachi Energy Ltd
18677332 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE Non-Final OA ROHM CO., LTD.
18757887 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE Non-Final OA STMicroelectronics International N.V.
18644231 INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAME Final Rejection TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18588069 INTEGRATED CIRCUIT (IC) STRUCTURES WITH THERMAL VIAS AND HEAT SPREADER LAYERS Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18459089 STRESS AND WARPAGE MODULATING STRUCTURE FOR MULTI-STACKED WAFER AND DIE LEVEL BONDING PACKAGES Final Rejection TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18177144 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
17887122 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18790273 CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18766246 COAXIAL THROUGH VIA WITH NOVEL HIGH ISOLATION CROSS COUPLING METHOD FOR 3D INTEGRATED CIRCUITS Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18602392 INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF Final Rejection TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
18327220 3D Stacking Structure and Method of Fabricating the Same Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.

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Frequently Asked Questions

What is examiner Erik J Kielin's allowance rate?

67.7% of resolved applications examined by Erik J Kielin were allowed (648 resolved cases), compared with 74.2% across Art Unit 2814 over the last five years.

Does an interview help with examiner Erik J Kielin?

This examiner's interview lift is +5.6 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner Erik J Kielin take to allow a patent?

Applications allowed by Erik J Kielin took 868 days on average from filing to allowance.

Which art unit does examiner Erik J Kielin work in?

Erik J Kielin examines applications in Art Unit 2814 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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