Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 10 and 19
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 5/24/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory device with row decoder having main word liner driver and sub word line driver.
Claim Objections
Independent claims 1 and 10 are objected to because of the following informalities: “a memory cell region comprising a plurality of word lines extending in the first horizontal direction and a plurality of bit lines extending in a second horizontal direction perpendicular to the first horizontal direction”. Here first direction is horizontal. So, the second direction, which is perpendicular to first direction, must be vertical direction. It can’t be a second horizontal direction.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 is rejected under 35 U.S.C. 103 as being unpatentable over Arimoto et al. (US 20030103368) in view of English et al. (US 20230333742).
Regarding independent claim 1, Arimoto discloses a memory device (Fig. 58) comprising:
a peripheral circuit structure (Fig. 58 shows peripheral units); and
a cell array structure provided on the peripheral circuit structure and overlapping the peripheral circuit structure in a vertical direction (Fig. 58 shows plurality of memory blocks MB0 to MBm arranged in vertical direction and overlapping peripheral circuit),
wherein the cell array structure comprises a plurality of memory blocks arranged in a first horizontal direction, at least one of the plurality of memory blocks (Figs. 58, 59) comprising:
a memory cell region comprising a plurality of word lines extending in the first horizontal direction and a plurality of bit lines extending in a second horizontal direction perpendicular to the first horizontal direction (Fig. 1 shows plurality of word lines extending in horizontal direction and plurality of bit lines extending in vertical direction),
wherein the peripheral circuit structure comprises a row decoder connected to the plurality of word lines of each of the plurality of memory blocks (Fig. 58 and [0442] describes row decoders are provided within local control circuits LCTL0 to LCTLm), and the row decoder comprises:
a first circuit group configured to generate main word line driving signals and sub word line driving signals, the first circuit group being commonly connected to the plurality of memory blocks (Figs. 1, 6 and [0165], [0179] describes that one main word line is provided to each set of 4 sub word lines. That is, one main word line is provided to a set of the sub word lines SWLL0, SWLR1, SWLL2 and SWLR3, and one main word line is also provided to a set of the sub word lines SWLL4, SWLR5, SWLL6 and SWLR7. Fig. 11 and [0206] describes main decode signal generating circuit 8 and sub decode signal generating circuit 7); and
a second circuit group respectively connected to the plurality of memory blocks and configured to generate local main word line driving signals and local sub word line driving signals (Fig. 69 and [0487] describes local control circuit and generating local word line drive timing signal and a local sub word line drive timing signal) and activate one word line from among a plurality of word lines of a memory block selected from among the plurality of memory blocks (Fig. 69 and [0487]).
Arimoto does not explicitly show wherein the cell array structure comprises a plurality of memory blocks arranged in a first horizontal direction;
However, English teaches wherein the cell array structure comprises a plurality of memory blocks arranged in a first horizontal direction (Fig. 1 and [0024] shows memory blocks 112A, 112B and so on are arranged in horizontal direction within memory bank 110).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of English to Arimoto in order to provide efficient methods and apparatuses for designing memory macro blocks as taught by English ([0004]).
Claims 10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Arimoto et al. (US 20030103368) in view of English et al. (US 20230333742) and He et al. (US 20140192598).
Regarding independent claim 10, Arimoto and English together disclose all the claim limitations of independent device claim 1, except:
wherein the peripheral circuit structure comprises a row decoder connected to even word lines and odd word lines of the plurality of word lines of the plurality of memory blocks,
However, He teaches wherein the peripheral circuit structure comprises a row decoder connected to even word lines and odd word lines of the plurality of word lines of the plurality of memory blocks (Fig. 1 and [0041] describes that memory cell array 10 includes a plurality of blocks, and, for example, odd-numbered blocks of all the blocks in the memory cell array 10 are connected to row decoder unit 12-1, while even-numbered blocks of all the blocks in the memory cell array 10 are connected to row decoder unit 12-2. Row decoder units 12-1 and 12-2 are connected to the plurality of word lines. Here examiner asserts that odd or even numbered blocks comprises both odd and even word lines).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of He to modified Arimoto in order to provide with row decoder configured to drive the word lines as taught by He ([0032]).
Regarding independent claim 19, and dependent claim 20, together they recite the same claim limitations from independent device claim 10 and henceforth rejected the same way.
Allowable Subject Matter
Claims 2-9 and 11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
“main word line driving signal generation circuit configured to generate first main word line driving signals and second main word line driving signals based on the row address signals that belong to the more significant bit group, wherein the main word line driving signals comprise the first main word line driving signals and the second main word line driving signals; and a sub word line driving signal generation circuit configured to generate first sub word line driving signals, second sub word line driving signals, and third sub word line driving signals based on the row address signals that belong to the less significant bit group among the row address signals, wherein the sub word line driving signals comprise the first sub word line driving signals, the second sub word line driving signals, and the third sub word line driving signals”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 12/31/2025