DETAILED ACTION
This Office Action is in response to Applicant’s Election dated 07/30/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Election was made without traverse in the reply filed on 07/30/2026.
Applicant’s election without traverse of claims 1-16 in the reply filed on 07/30/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5, 7 and 9-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
► With respect to claim 3,
It is not clear “where each first semiconductor structure comprises a silicon nanosheet layer sandwiched between an upper oxide layer and a lower oxide layer, where the upper and lower oxide layers are each formed with annealed implanted oxygen.” refers to which process step of method of claim 1. Applicant is respectfully suggested to clarify and use appropriate claim language to define scope of claim.
► With respect to claim 4,
It is not clear ” where each first semiconductor structure comprises a silicon nanosheet layer sandwiched between an upper ALD oxide layer and a lower ALD oxide layer.” refers which process step of method of claim 1. Applicant is respectfully suggested to clarify and use appropriate claim language to define scope of claim.
► With respect to claim 7,
It is not clear “the one or more first planar semiconductor channel layers…equals the one or more second planar semiconductor channel layers…” refers to which process step of method of claim 1. In addition, it is not which claimed characteristics of the one or more first planar semiconductor channel layers equals to which claimed characteristics of the
one or more second planar semiconductor channel layers. Applicant is respectfully suggested to clarify and use appropriate consistent claimed language to define scope of claim.
► With respect to claim 9,
Lines 8-12, “processing the I/O nanosheet transistor stack to form conductive terminal structures adjacent to the I/O nanosheet transistor stack and to form a gate-all-around electrode around at least three sides of each first nanosheet structure in the I/O nanosheet transistor stack which are connected between the conductive terminal structures formed on opposite sides of the patterned nanosheet stack,” renders the claim indefinite. It is not clear which claimed element being connected between the conductive terminal structures – the I/O nanosheet transistor stack or a gate-all-around electrode? In addition, “the patterned nanosheet stack” lacks antecedent basic. It is not clear where “the patterned nanosheet stack” comes from, locates and includes which claimed element(s).
Lines 13-15, “where each gate-all-around electrode formed in the I/O nanosheet transistor stack is connected over a gate dielectric layer and the upper dielectric layer and lower dielectric layer to control the planar semiconductor channel layer in the I/O nanosheet transistor stack.” renders the claim indefinite. It is not clear what “is connected over” means. It is not clear how each gate-all-around electrode is connected the upper dielectric layer and the lower dielectric layer while each gate-all-around electrode is connected “a gate dielectric layer”
Allowable Subject Matter
Claims 1-2, 6 and 8 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANHHA S PHAM whose telephone number is (571)272-1696. The examiner can normally be reached Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANHHA S PHAM/Primary Examiner, Art Unit 2812
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