Prosecution Insights
Last updated: April 19, 2026
Application No. 18/674,351

COIL STRUCTURE AND METHOD OF MAKING SAME

Non-Final OA §103
Filed
May 24, 2024
Examiner
MOURAD, RASEM
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
392 granted / 531 resolved
+5.8% vs TC avg
Strong +26% interview lift
Without
With
+26.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
22 currently pending
Career history
553
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
60.4%
+20.4% vs TC avg
§102
17.4%
-22.6% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 531 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Objections Claims 5, 10, 11, 17 objected to because of the following informalities: Claim 5 recites “…in a honeycomb pattern to cover more than 90% of the surface of the substrate.” This should instead be “91%” (see par [0013] of published disclosure). Claim 10 recites “an second encapsulating material”. It should be “a second encapsulating material.” Claim 10 recites “a second dielectric layer on the topmost surface of the encapsulating material and the respective topmost surfaces of the plurality of conductive coils.” The “second dielectric layer” should be “a fourth dielectric layer” on the topmost surface of the “second encapsulating material” and the respective topmost surfaces of the second plurality of conductive coils.” Claim 11 recites “… a plurality of coils arranged on the wafer such that a center point of each coil is equidistant form a magnetic field focal point…” “form” should be corrected to “from”. Claim 17 recites “…forming a patterned layer…when view in top-down view…” It should be “when viewed in top-down view…” Claim 17 recites “…patterning the second dielectric layer expose portions of respective coils…” This should be corrected to “…patterning the second dielectric layer to expose portions of respective coils…” Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. (2015/0222144 A1) in view of Jiang et al. (2011/0291231 A1). Regarding Claim 1, Iwasaki teaches a device comprising: a battery (4); a charging integrated circuit (par [48]; the rectifier circuitry 102, the linear regulator 106, and the controller 108 are integrated on single semiconductor substrate as function IC (Integrated circuit)”), the charging integrated circuit configured to convert received AC power into DC power (pars [48-49] and related discussion; the rectifier 102 of the integrated circuit is “configured to” convert AC power S1 into DC power as is well-known and well-understood); a power receiving coil structure (6) configured to receive AC power and feed the AC power to the charging integrated circuit (pars [48-49]; receiving coil 6 receives AC power S1 and feeds it to the charging integrated circuit). Iwasaki does not explicitly disclose a coil structure including a substrate, a plurality of conductive coils disposed over the substrate, a dielectric layer interjacent the substrate and the plurality of conductive coils, an encapsulating material covering respective sidewalls of the plurality of conductive coils, the encapsulating material having a planar topmost surface that is level with respective topmost surfaces of the plurality of conductive coils; and a second dielectric layer on the topmost surface of the encapsulating material and the respective topmost surfaces of the plurality of conductive coils. Jiang, however, teaches it is known for a coil structure to include a substrate (160, par [103]), a plurality of conductive coils (see figs.26, 31 for e.g., items 403, 425) disposed over the substrate (see fig. 31, 160); a dielectric layer (164, par [108]) interjacent the substrate (160) and the plurality of conductive coils (see fig. 31); an encapsulating material (par [108]; encapsulating material of lower item 190 between the bottommost surfaces of coils 403, 425 and level with the topmost surfaces of coils 403, 425) covering respective sidewalls of the plurality of conductive coils (see fig.31, lower layer of item 190 covers the sidewalls of the conductive coils), the encapsulating material having a planar topmost surface that is level with respective topmost surfaces of the plurality of conductive coils (fig.31, lower layer of item 190 is level with the respective topmost surfaces of the coils. Examiner Note: Yamazaki (2007/0166954), fig.6C, par [89]; shows how the encapsulating material in Jiang would have a planar topmost surface level with respective topmost surface of coil 20); and a second dielectric layer (top layer of item 190 between the topmost surfaces of coils 403, 425, the encapsulating material and 192) on the topmost surface of the encapsulating material and the respective topmost surfaces of the plurality of conductive coils (see fig.31; top layer of 190 is on the topmost surfaces of the encapsulating material of lower layer of 190 that is level with topmost surfaces of the coils). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Iwasaki to that of Jiang. The motivation would have been to build the coil of Iwasaki using a known way to make a coil with a reasonable expectation of success. Regarding Claim 10, Modified Iwasaki teaches the claimed subject matter in claim 1 and further teaches a power transmitting circuit (Iwasaki, fig.1, item 2) including a microcontroller (Iwasaki, fig.1, 9) and a power transmitting coil (Iwasaki, fig.1, 7). Iwasaki does not explicitly disclose the power transmitting coil including a second substrate; a second plurality of conductive coils disposed over the second substrate; a third dielectric layer interjacent the second substrate and the second plurality of conductive coils; an second encapsulating material covering respective sidewalls of the second plurality of conductive coils, the second encapsulating material having a planar topmost surface that is level with respective topmost surfaces of the second plurality of conductive coils; and a second dielectric layer on the topmost surface of the encapsulating material and the respective topmost surfaces of the plurality of conductive coils. Jiang, however, similar to claim 1’s making of a power receiving coil, teaches it is known for a coil structure to include a second substrate (160, par [103]), a second plurality of conductive coils (see figs.26, 31 for e.g., items 403, 425) disposed over the second substrate (see fig. 31, 160); a third dielectric layer (164, par [108]) interjacent the second substrate (160) and the second plurality of conductive coils (see fig. 31); an second encapsulating material (par [108]; encapsulating material of lower item 190 between the bottommost surfaces of coils 403, 425 and level with the topmost surfaces of coils 403, 425) covering respective sidewalls of the plurality of the second plurality of conductive coils (see fig.31, lower layer of item 190 covers the sidewalls of the conductive coils), the second encapsulating material having a planar topmost surface that is level with respective topmost surfaces of the second plurality of conductive coils (fig.31, lower layer of item 190 is level with the respective topmost surfaces of the coils. Examiner Note: Yamazaki (2007/0166954), fig.6C, par [89]; shows how the encapsulating material in Jiang would have a planar topmost surface level with respective topmost surface of coil 20); and a second dielectric layer (top layer of item 190 between the topmost surfaces of coils 403, 425, the encapsulating material and 192) on the topmost surface of the encapsulating material and the respective topmost surfaces of the plurality of conductive coils (see fig.31; top layer of 190 is on the topmost surfaces of the encapsulating material of lower layer of 190 that is level with topmost surfaces of the coils). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Iwasaki to that of Jiang. The motivation would have been to build the transmitter coil of Iwasaki using a known way to make a coil with a reasonable expectation of success. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. (2015/0222144 A1) in view of Jiang et al. (2011/0291231 A1) in further view of Cooney, III et al. (2012/0319237 A1). Regarding Claim 2, The combination teaches the claimed subject matter in claim 1. While the combination teaches the dielectric layer and the second dielectric layer both comprise TEOS material. The combination does not explicitly disclose a dielectric layer comprises an inorganic material. Cooney, III, however, teaches it is known for a dielectric layer to comprise an inorganic material (par [28]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination’s dielectric layers to comprise an inorganic material. The motivation would have been because the combination, specifically Jiang, states that the type of material for the first and second dielectric materials is not a limitation (Jiang, pars [64, 69]) and thus one skilled in the art would have resorted to other well-known and well-desired materials, such as an inorganic material, for both the first and second dielectric layers. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. (2015/0222144 A1) in view of Jiang et al. (2011/0291231 A1) in further view of Elian et al. (2014/0097514 A1). Regarding Claim 3, The combination teaches the claimed subject matter in claim 1 and further teaches the dielectric layer and the second dielectric layer both comprise TEOS material (Jiang, pars [64, 69]). The combination does not explicitly disclose a dielectric layer comprises a polymer. Elian, however, teaches it is known for a dielectric layer to comprise a polymer (par [52]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination’s dielectric layers to comprise a polymer. The motivation would have been because the combination, specifically Jiang, states that the type of material for the first and second dielectric materials is not a limitation (Jiang, pars [64, 69]) and thus one skilled in the art would have resorted to other well-known and well-desired materials, such as a polymer, for both the first and second dielectric layers. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. (2015/0222144 A1) in view of Jiang et al. (2011/0291231 A1) in further view of Kitajima et al. (2016/0336110 A1). Regarding Claim 4, The combination teaches the claimed subject matter in claim 1 and further teaches the encapsulating material comprises TEOS material (par [64]). The combination does not explicitly disclose the encapsulating material comprises a polymer. Kitajima, however, teaches it is known in the art for the encapsulating material to comprise a polymer (par [106]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination’s encapsulating material to comprise a polymer. The motivation would have been because the combination, specifically Jiang, states that the type of encapsulating material is not a limitation (Jiang, par [64]) and thus one skilled in the art would have resorted to other well-known and well-desired materials, such as a polymer, as discussed within Kitajima for the encapsulating material. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. (2015/0222144 A1) in view of Jiang et al. (2011/0291231 A1) in further view of Partovi et al. (2009/0096413 A1). Regarding Claim 5, The combination teaches the claimed subject matter in claim 5. The combination does not explicitly disclose wherein the plurality of conductive coils are arranged in a honeycomb pattern to cover more than 90% of the surface area. Patovi (fig.13), however, teaches the plurality of conductive coils (312) are arranged in a honeycomb pattern (see fig.13, par [195]) to cover more than 90% of the surface (fig.13, par [195]; the area of the surface in which coils 312 are arranged covers more than 90%/the full area). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination to that of Partovi of arranging the plurality of conductive coils in a honeycomb pattern. The motivation would have been to build a well-known and well-desired coil pattern in the honeycomb pattern as discussed within Partovi and further noting that a honeycomb coil pattern is an obvious design choice to one skilled in the art. Allowable Subject Matter Claims 6-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record, taken alone or in combination, does not teach “first electrical connectors extending through the second dielectric layer, respective first electrical connectors contacting respective first ends of respective conductive coils, and second electrical connectors extending through the second dielectric layer, respective second electrical connectors contacting respective second ends of respective conductive coils.” Claims 7-9 depend on claim 6 and are therefore indicated as allowable for similar reasons. Claims 11-20 allowed. The following is a statement of reasons for the indication of allowable subject matter: With respect to independent claim 11, the prior art of record, taken alone or in combination, does not teach the particular limitations of the device as claimed including “a power transmitting circuit including a power transmitting coil; and a power receiving circuit including a power receiving coil; wherein at least one of the power transmitting coil and the power receiving coil includes a wafer, a plurality of coils arranged on the wafer such that a center point of each coil is equidistant from a magnetic field focal point located a predetermined distance from a major surface of the wafer, wherein each coil includes a conductive spiral structure sandwiched between a first dielectric layer and a second dielectric layer, and further wherein each coil has sidewalls encapsulated within an encapsulant that is also sandwiched between the first dielectric layer and the second dielectric layer; a plurality of first electrical connectors, respective first electrical connectors extending through the second dielectric layer and contacting respective first ends of respective coils, and a plurality of second electrical connectors, respective second electrical connectors extending through the second dielectric layer and contacting respective second ends of respective coils.” Claims 12-16 depend on claim 11 and are therefore indicated as allowable for similar reasons. With respect to independent claim 17, the prior art of record, taken alone or in combination, does not teach the particular steps of forming a device including “depositing a first dielectric layer over a substrate; forming a patterned layer on the first dielectric layer, the patterned layer including a plurality of coil-shaped openings when viewed in top-down view; filling the coil-shaped openings with conductive material to form a plurality of coils on the first dielectric layer, and removing the patterned layer; encapsulating the plurality of coils in an encapsulating material, wherein a topmost surface of the encapsulating material is level with respective topmost surfaces of respective coils of the plurality of coils; depositing a second dielectric layer over the encapsulating material and the plurality of coils; patterning the second dielectric layer to expose portions of respective coils; and forming respective electrical connections to respective coils within the patterned second dielectric layer.” Claims 18-20 depend on claim 17 and are therefore indicated as allowable for similar reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RASEM MOURAD whose telephone number is (571)270-7770. The examiner can normally be reached M-F 9:00-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at (571)272-7492. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RASEM MOURAD/Examiner, Art Unit 2836 /REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836
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Prosecution Timeline

May 24, 2024
Application Filed
Mar 04, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+26.2%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 531 resolved cases by this examiner. Grant probability derived from career allow rate.

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