Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SHIELDING LINES WITHIN BIT LINE INTERCONNECTION STRUCTURES AND SEMICONDUCTOR MEMORY DEVICES COMPRISING THE SAME
Claim Objections
Claim 11 objected to because of the following informalities: “second conductive lines arranged along a first lateral direction” should be “second conductive lines arranged along the first lateral direction” to avoid antecedent uncertainty. Based upon the specification, the Examiner has interpreted the limitation as the first lateral direction.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3 and 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “wherein the first interconnection structure is connected between bit lines of adjacent arrays of vertical transistors”. The Examiner cannot determine the scope of “connected between”. For example, it is unclear whether the limitation requires that one or more bit lines from each of adjacent arrays are connected to one another by the first interconnection structure, whether the interconnection structure is located between bit lines of each of adjacent arrays but does not connect bit lines with one another, or whether another requirement is intended. In reviewing Figs 7 and 8, and associated description, the Examiner is uncertain exactly what portion(s) of the structure and connection(s) are being referred to.
In the claim rejections below, one interpretation is included.
Claim 13 recites “wherein the first interconnection structure is connected between bit lines of adjacent arrays of vertical transistors”. The Examiner cannot determine the scope of “connected between”. For example, it is unclear whether the limitation requires that one or more bit lines from each of adjacent arrays are connected to one another by the first interconnection structure, whether the interconnection structure is located between bit lines of each of adjacent arrays but does not connect bit lines with one another, or whether another requirement is intended. In reviewing Figs 7 and 8, and associated description, the Examiner is uncertain exactly what portion(s) of the structure and connection(s) are being referred to.
In the claim rejections below, one interpretation is included.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 9-11, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee; Kiseok et al. (US 2024/0147701; hereinafter Lee).
Regarding claim 1, Lee discloses a semiconductor device (in particular, Figs 1A,3A-3C; ¶ [0091-100,0019-89], entire document), comprising:
a memory array structure (CS in CAR; Figs 1A,3A-3C; ¶ [0091-92,0021]) comprising:
a transistor layer comprising a plurality of arrays of vertical transistors (VCT; ¶ [0092]),
a storage layer (DSP; Figs 3A-3B; ¶ [0076-77,0099]) comprising a plurality of arrays of capacitors (¶ [0099]) coupled with the vertical transistors,
a plurality of bit lines (BL; Figs 1A,3A-3C; ¶ [0098-99]) coupled with the vertical transistors, and
a first interconnection layer (layers above STI and below 263 in BCR and WCR; Figs 3A-3C; ¶ [0091-92,0021]) comprising a first interconnection structure (241a,PCPd; Figs 3A-3B; ¶ [0086]) connected with the plurality of bit lines, and a second interconnection structure (PCPb,241b; Fig 3C; ¶ [0086]) disconnected with the plurality of bit lines and connected to a common electrical node (173b; Figs 3A-3C,2B; ¶ [0080,0032]); and
a peripheral circuit structure (the structure besides the memory array structure {besides CS in CAR; that is, PS, CS in BCR, and CS in WCR}; Figs 3A-3C; ¶ [0091-98]) connected with the memory array structure, and comprising:
a second interconnection layer (layers below 211 in BCR and WCR; Figs 3A-3C; ¶ [0091-98) comprising a third interconnection structure (PCL,PCT; Fig 3A; ¶ [0098]) connected with the first interconnection structure (Fig 3A; ¶[0098]), and
a sense amplifier circuit connected with the third interconnection structure (PC may include sense amplifiers {¶ [0095} and is connected with PCT; Fig 3A).
Regarding claim 2, Lee discloses the semiconductor device of claim 1, wherein the second interconnection layer (layers below 211 in BCR and WCR; Figs 3A-3C) further comprises:
a fourth interconnection structure (PCPb, and the end portion of 173 in WCR; Fig 3C; ¶ [0080,0031]) disconnected with the sense amplifier circuit and the first interconnection structure, and connected to the common electrical node (173b/173; Fig 3C).
Regarding claim 4, Lee discloses the semiconductor device of claim 1, wherein the first interconnection structure (layers above STI and below 263 in BCR and WCR; Figs 3A-3C) comprises:
a plurality of first conductive lines (241a; Figs 3A-3B; ¶ [0088]) arranged along a first lateral direction (D1; reference Fig 1A and the bit lines BL, which are arranged in the same direction as 241a {shown in Fig 3A}), each first conductive line extends along a second lateral direction (D2) and is coupled with a corresponding one of the bit lines (BL; Figs 1A,3A-3C) through a bit line contact structure (PCPa; Figs 3A-3B; ¶ [0080]).
Regarding claim 9, Lee discloses the semiconductor device of claim 2, wherein:
the second interconnection layer (layers below 211 in BCR and WCR; Figs 3A-3C) comprises at least two layers of conductive lines (PCL and the end portion of 173 in WCR; Fig 3C); and
the third interconnection structure (PCL,PCT; Fig 3A) and the fourth interconnection structure (PCPb, and the end portion of 173 in WCR; Fig 3C) are portions of the at least two layers of conductive lines.
Regarding claim 10, Lee discloses the semiconductor device of claim 1, wherein the memory array structure (CS in CAR; Figs 1A,3A-3C) further comprises:
first bit line contact structures (PCPa; Figs 3A-3B; ¶ [0080]) located at a first side of a corresponding array of vertical transistors (upper side of CAR; Fig 1A), and in contact with odd bit lines of the corresponding array of vertical transistors (in contact with the first, third, and fifth bit line BL as shown in Fig 1A); and
second bit line contact structures (PCPa; Figs 3A-3B; ¶ [0080]) located at a second side of the corresponding array of vertical transistors opposite to the first side (lower side of CAR; Fig 1A), and in contact with even bit lines of the corresponding array of vertical transistors (in contact with the second and forth bit line BL as shown in Fig 1A).
Regarding claim 11, Lee discloses a semiconductor device (in particular, Figs 1A,3A-3C; ¶ [0091-100,0019-89], entire document), comprising:
vertical transistors (VCT; ¶ [0099]);
bit lines (BL; Figs 1A,3A-3C; ¶ [0098-99]) coupled with the vertical transistors;
a first interconnection structure (241a, 241b; Figs 3A-3B; Figs 3A-3C; ¶ [0086]) comprising:
first conductive lines (241a; Figs 3A-3B; ¶ [0088]) arranged along a first lateral direction (D1; reference Fig 1A and the bit lines BL, which are arranged in the same direction as 241a), each first conductive line extending along a second lateral direction (D2) and being connected with a corresponding one of the bit lines (connected through PCPa; Figs 3A-3B; ¶ [0085-86]), and
second conductive lines (241b; Figs 3C; ¶ [0088]) arranged along the first lateral direction, each second conductive line extending along the second lateral direction and being connected to a common electrical node (173b connected through PCPb to 241b; Figs 3C; ¶ [0080,0086,0032]) and disconnected with the bit lines (as shown in Figs 3A-3C and associated description; separated from the bit lines at least by 171; Fig 3C; ¶ [0027]); and
a sense amplifier circuit connected with the bit lines through the first conductive lines (BL connects through PCPa to 241a to PCPd to peripheral circuits PC {Fig 3A and associated description}, and PC may include sense amplifiers {¶ [0095}).
Regarding claim 20, Lee discloses the semiconductor device of claim 11, further comprising:
first bit line contact structures (PCPa; Figs 3A-3B; ¶ [0080]) located at a first side of a corresponding array of vertical transistors (upper side of CAR; Fig 1A), and in contact with odd bit lines of the corresponding array of vertical transistors (in contact with the first, third, and fifth bit line BL as shown in Fig 1A); and
second bit line contact structures (PCPa; Figs 3A-3B; ¶ [0080]) located at a second side of the corresponding array of vertical transistors opposite to the first side (lower side of CAR; Fig 1A), and in contact with even bit lines of the corresponding array of vertical transistors (in contact with the second and forth bit line BL as shown in Fig 1A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 8, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee; Kiseok et al. (US 2024/0147701; hereinafter Lee) in view of Choi; Hyungeun et al. (US 2025/0167107; hereinafter Choi).
Regarding claim 3, Lee discloses the semiconductor device of claim 1, wherein the first interconnection structure (241a,PCPd; Figs 1A,3A-3B) is connected in bit line connection region BCR outside the cell array region CAR (as show in Fig 1A; ¶ [0021,0024]).
Lee does not disclose another cell array region (array of vertical transistors) where the first interconnection structure is connected between bit lines of adjacent arrays of vertical transistors; however, configurations including a plurality of cell array regions with bit line connection region(s) between them is known in the art. See, for example, Choi Fig 4A which depicts bit line contacts BL1C,BL2C (¶ 0062]) connected to interconnection structures (160,170) in an extension region ER2 (¶ [0030]) between adjacent arrays of cell transistors cTR (¶ [0039]). Accordingly, it would have been obvious to have combined the semiconductor device of Lee with the multiple cell array regions of Choi such that the first interconnection structure is connected between bit lines of adjacent arrays of vertical transistors. One would have been motivated to do this in order to manage a variety of performance and architectural requirements well-known in the art, such as parallel processing, data access speed, and power consumption. One would have had a reasonable expectation of success because the structure of Lee is suitably configured with the first interconnection structure at outside edges of the vertical transistor array, and because the further limitation of Claim 3 is one well-known in the art.
Regarding claim 8, Lee discloses the semiconductor device of claim 1, wherein:
the first interconnection layer (layers above STI and below 263 in BCR and WCR; Figs 3A-3C) comprises at least one layer of conductive lines (241a,241b; Figs 3A-3C); and
the first interconnection structure (241a,PCPd; Figs 3A-3B) and the second interconnection structure (PCPb,241b; Fig 3C) are portions of the at least one layer of conductive lines.
Lee does not disclose the at least one layer comprises at least two layers.
In the same field of endeavor, Choi discloses an interconnection layer of a similar memory array structure (router lower structure RT1b1; ¶ [0094]) which comprises at least two layers (160,170; Fig 4C; ¶ [0094-96]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the first interconnection layer of Claim 1 may comprise at least two layers. One may have been motivated to configure the layer this way in order to a manage a variety of performance, reliability, and/or manufacturing constraints, and would have had a reasonable expectation of success because of the similarity in structure and signal path of the interconnection layers of Lee and Choi and because such line routing optimizations are well-known and common in the art.
Regarding claim 13, Lee discloses the semiconductor device of claim 11, wherein the first interconnection structure is connected in bit line connection region BCR outside the cell array region CAR (as show in Fig 1A; ¶ [0021,0024]).
Lee does not disclose another cell array region (array of vertical transistors) where the first interconnection structure is connected between bit lines of adjacent arrays of vertical transistors; however, configurations including a plurality of cell array regions with bit line connection region(s) between them is known in the art. See, for example, Choi Fig 4A which depicts bit line contacts (interconnection structures) BL1C,BL2C (¶ 0062]) in an extension region ER2 (¶ [0030]) between adjacent arrays of cell transistors cTR (¶ [0039]). Accordingly, it would have been obvious to have configured the semiconductor device of Lee with multiple cell array regions such that the first interconnection structure is connected between bit lines of adjacent arrays of vertical transistors. One would have been motivated to do this in order to manage a variety of performance and architectural requirements well-known in the art, such as parallel processing, data access speed, and power consumption. One would have had a reasonable expectation of success because the structure of Lee is suitably configured with the first interconnection structure at the edges of the vertical transistor array, and because the further limitation of Claim 3 is one well-known in the art.
Regarding claim 18, Lee discloses the semiconductor device of claim 11, but does not disclose wherein the first conductive lines (241a; Figs 3A-3B) and the second conducive lines (241b; Figs 3C) are distributed in at least two conductive wiring layers along a vertical direction.
In the same field of endeavor, Choi discloses an interconnection structure of a similar memory array structure (router lower structure RT1b1; ¶ [0094]) which comprises at least two layers (160,170; Fig 4C; ¶ [0094-96]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the first conductive lines and the second conducive lines of Claim 11 may be distributed in at least two conductive wiring layers along a vertical direction. One may have been motivated to configure the lines this way in order to a manage a variety of performance, reliability, and/or manufacturing constraints, and would have had a reasonable expectation of success because of the similarity in structures of Lee and Choi and because such line routing optimizations are well-known and common in the art.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee; Kiseok et al. (US 2024/0147701; hereinafter Lee) in view of Lee; Kiseok et al. (US 2023/0363143; hereinafter Lee143) and Miyazaki; Takayuki (US 2018/0151200; hereinafter Miyazaki).
Regarding claim 12, Lee discloses the semiconductor device of claim 11, further comprising a second interconnection structure (PCL,PCT, end portion of 173 in WCR; Figs 3A-3B) comprising:
third conductive lines (PCL,PCT; Figs 3A-3B; ¶ [0098]) connected between the first conductive lines (241a; Figs 3A-3B) and the sense amplifier circuit (PC; Figs 3A-3B); and
a conductive plate (end portion of 173 in WCR; Fig 3C; ¶ [0080,0031]) connected to the common electrical node (173b; Figs 3C,2B), and disconnected with the sense amplifier circuit and the first interconnection structure.
Lee does not disclose fourth conductive lines connected to the common electrical node, and disconnected with the sense amplifier circuit and the first interconnection structure.
In the same field of endeavor, Lee143 discloses a similar semiconductor device comprising shielding lines 173/174 Figs 1A-1C; ¶ [0031-32]) in place of the shielding conductive pattern 173{173a/173b} of Lee, wherein each shielding line (conductive line) is disconnected with a corresponding sense amplified circuit and first interconnection structure. Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the structures of Lee143 and Lee, such that the second interconnection structure of Lee comprises fourth conductive lines (Lee143; 173/174; Fig 1C) disconnected with the sense amplifier circuit and the first interconnection structure. One would have been motivated to do this in order to combine the alternate shielding configuration of Lee143 with the structure of Lee having a peripheral portion PS connected below a cell array structure CS. One would have had a reasonable expectation of success because of the similarity in structure and configuration of the semiconductor devices of Lee and Lee143.
Lee143 does not disclose that the shielding lines are connected to a common electrical node; however, this would have been obvious to a person having ordinary skill in the art in order for the shielding lines to perform their function. For example, Miyazaki discloses bit line shielding lines connected with ground voltage or another fixed voltage (¶ [0205]).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee; Kiseok et al. (US 2024/0147701; hereinafter Lee) in view of Lee; Kiseok et al. (US 2023/0363143; hereinafter Lee143).
Regarding claim 14, Lee discloses the semiconductor device of claim 11, but does not disclose wherein each first conductive line (241a; Figs 3A-3B) is aligned with a corresponding one of the second conductive lines (241b; Fig 3C); along the second lateral direction.
In the same field of endeavor, Lee143 discloses a similar semiconductor device comprising shielding lines 173/174 Figs 1A-1C; ¶ [0031-32]) in place of the shielding conductive pattern 173{173a/173b} of Lee, wherein each shielding line is connected with a second conductive line (Lee143; 241b; Fig 1C; ¶ [0085]), and is aligned with a corresponding first conductive line (Lee143; 241a; as shown by Fig 1C; ¶ [0085]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the structures of Lee143 and Lee, satisfying the limitation of Claim 14. One would have been motivated to do this in order to combine the alternate shielding configuration of Lee143 with the structure of Lee having a peripheral portion PS connected below a cell array structure CS. One would have had a reasonable expectation of success because of the similarity in structure and configuration of the semiconductor devices of Lee and Lee143.
Allowable Subject Matter
Claims 5-7, 15-17, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5-7, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein adjacent first conductive lines have different first lengths along the second lateral direction” in combination with the additional limitations of the independent and intervening claims.
Regarding claims 15-17, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein adjacent first conductive lines have different first lengths along the second lateral direction” in combination with the additional limitations of the independent and intervening claims.
Regarding claims 19, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the fourth conducive lines are distributed in at least two conductive wiring layers along a vertical direction” in combination with the additional limitations of the independent and intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim; Seunghoon et al. (US 2025/0220894; the prior art discloses a memory device with bit line shielding lines having one of several exemplary configurations and bit line interconnection structures having conductive lines on multiple layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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