Prosecution Insights
Last updated: May 29, 2026
Application No. 18/674,569

STORAGE DEVICE FOR PERFORMING REFRESH OPERATION AND OPERATING METHOD THEREOF

Final Rejection §103
Filed
May 24, 2024
Priority
Dec 05, 2023 — RE 10-2023-0174153
Examiner
BEGUM, SULTANA
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
498 granted / 534 resolved
+25.3% vs TC avg
Minimal +0% lift
Without
With
+0.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
20 currently pending
Career history
556
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
82.7%
+42.7% vs TC avg
§102
4.2%
-35.8% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 534 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of claim(s) to be treated in this office action: a. Independent: 1, 13 and 17 b. Pending: 1-9, 11-18 Claims 10 and 19 have been canceled. Claims 1, 11, 13 and 17 have been amended. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Claim Objections Claim 13 is objected to because of the following informalities: New added word “and” is written with uppercase “A”. Appropriate correction is required. Specification The new title is reviewed and accepted. Amended paragraphs [0009], [0040], [0067] and [0073] have been reviewed and accepted. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 11049547) in view of Lin et al. (US 20160350179). Regarding independent claim 13, Lee discloses a method of operating a storage device (Figs. 1, 9), the method comprising: sequentially applying a plurality of threshold voltage detecting voltages to a plurality of word lines coupled to a memory block (Fig. 9 shows applying voltage of first level to first word line at step $220 and then sequentially apply voltage of second level to second word line at step $280); acquiring read data corresponding to each of the plurality of threshold voltage detecting voltages (Fig. 9 shows determining read voltages); detecting a threshold voltage distribution of the memory block on the basis of the read data (Fig. 9 at steps $240 and $260 shows distribution based on read data); and determining a degree of deterioration of retention characteristics of the memory block on the basis of the threshold voltage distribution (Fig. 6 at steps $120 and $140 describes determining degree of degradation); And Further Lin teaches determining whether to perform a weak word line read operation on the memory block on the basis of the threshold voltage distribution ([0083] describes that memory management circuit 702 determines the first soft-decision read voltage level and the second soft-decision read voltage level according to a voltage distribution state (i.e., a threshold voltage distribution state) of the first memory cells). It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lin to Lee in order to provide with decoding method, a memory storage device and a memory control circuit unit, which are capable of improving a decoding efficiency of block codes as taught by Lin ([0009]). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 11049547) in view of Lin et al. (US 20160350179) and Lue et al. (US 20200192971). Regarding claim 14, Lee and Lin together disclose all the elements of claim 13 as above and through Lue further the detecting the threshold voltage distribution comprises: determining a number of strings, from among a plurality of strings, that have a lower or higher threshold voltage than each of the plurality of threshold voltage detecting voltages, each string including a plurality of memory cells coupled to the plurality of word lines on the basis of the read data; and detecting the threshold voltage distribution on the basis of voltage levels of the plurality of threshold voltage detecting voltages and the determined number of strings (Fig. 11 and [0088] describes applying a computation level word line voltage to the word line or word lines at the selected word line level k. [0095] describes that number of bit lines (equivalent to strings) and string select lines used for a given computation can be logically determined in each cycle of the operation). It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lue to modified Lee in order to provide a dense and energy-efficient multiply-and-accumulate accelerator as taught by Lue ([0023]). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 11049547) in view of Lin et al. (US 20160350179) and Jeong et al. (US 20190348103). Regarding claim 15, Lee and Lin together disclose all the elements of claim 13 as above and through Jeong further determining a read voltage to be used in a refresh operation on the memory block on the basis of the degree of the deterioration of the retention characteristics ([0049] and claim 8 states that based on number of bit lines refresh operation would take place). It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Jeong to modified Lee in order to properly predict refresh timing of accurate bit line as taught by Jeong ([0082]). Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 11049547) in view of Lin et al. (US 20160350179) and Lue et al. (US 20200192971) and Jeong et al. (US 20190348103). Regarding claim 16, Lee and Lin together disclose all the elements of claim 13 as above and through Lue further determining a number of strings, from among a plurality of strings, having a lower threshold voltage than a detecting voltage ([0095] describes that number of bit lines (equivalent to strings) and string select lines used for a given computation can be logically determined in each cycle of the operation), each including a plurality of memory cells coupled to the plurality of word lines (Figs. 3, 5-6, 8 shows NAND block array with multiple strings and memory cells) on the basis of read data corresponding to the detecting voltage; and Jeong teaches determining whether to perform a refresh operation on the memory block on the basis of the determined number of strings ([0049] and claim 8 states that based on number of bit lines refresh operation would take place). It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lue and Jeong to modified Lee in order to provide a dense and energy-efficient multiply-and-accumulate accelerator as taught by Lue ([0023]) and to properly predict refresh timing of accurate bit line as taught by Jeong ([0082]) respectively. Allowable Subject Matter Claims 1-9, 11-12 and 17-18 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Independent claims 1 and 17 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: “memory controller determines whether to perform a weak word line read operation on the memory block based on the determined number of strings”; for independent claim 1; and “memory controller performs a weak word line read operation on the memory block according to the determined number of first strings and the determined number of second strings and determines whether to perform the refresh operation on the basis of read data acquired by the weak word line read operation”; for independent claim 17 respectively. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SULTANA BEGUM/Primary Examiner, Art Unit 2824 4/4/2026
Read full office action

Prosecution Timeline

May 24, 2024
Application Filed
Dec 02, 2025
Non-Final Rejection mailed — §103
Jan 30, 2026
Interview Requested
Feb 13, 2026
Examiner Interview Summary
Feb 13, 2026
Applicant Interview (Telephonic)
Feb 27, 2026
Response Filed
Apr 08, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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DETERMINATION OF A BIAS VOLTAGE TO APPLY TO ONE OR MORE MEMORY CELLS IN A NEURAL NETWORK
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LOW ERROR RATE READ OPERATION IN MULTI-MODULE ARRAYS
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Patent 12620427
STORAGE DEVICE AND DRIVING METHOD OF STORAGE DEVICE BASED ON ADDRESS CONVERSION
2y 2m to grant Granted May 05, 2026
Patent 12609158
MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR DATA CALCULATION WITH THE MEMORY DEVICE
2y 3m to grant Granted Apr 21, 2026
Patent 12609149
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1y 11m to grant Granted Apr 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
94%
With Interview (+0.4%)
1y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 534 resolved cases by this examiner. Grant probability derived from career allowance rate.

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