Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species III (FIGS. 6A-6B, corresponding to claims 1-2 and 4-20) in the reply filed on 08/21/2026 is acknowledged.
Claim Objections
Claims 3-4 objected to because of the following informalities: because they have belonged to the withdrawn claim 2. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-7, 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (Pub. No.: US 2017/0345843) in view of LEE (Pub. No.: 2019/0333929) and further in view of IIJIMA (Pub. No.: US 2021/0296277).
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Re claim 1, Re claim 1, Lee, FIG. 9 [as shown above] teaches a semiconductor device, comprising:
a second bit line (BL);
a source conductive layer (150, [0053]);
a plurality of first gate electrodes (121 of (120a1)) between the first bit line and the source conductive layer, stacked in a first direction perpendicular to an upper surface of the first bit line and spaced apart from each other;
a first channel structure (CH1) penetrating the plurality of first gate electrodes (121 of (120a1)) and including a first channel semiconductor layer electrically connected to the first bit line;
a plurality of second gate electrodes (121 of (120a2)) between the source conductive layer and the second bit line (BL), stacked in the first direction and spaced apart from each other; and
a second channel structure (CH2) penetrating the plurality of second gate electrodes and including a second channel semiconductor layer electrically connected to the second bit line, wherein the plurality of first gate electrodes (121 of (120a1)) are in a height level lower than a height level of a lower surface of the source conductive layer (150), and the plurality of second gate electrodes (121 of (120a2)) are in a height level higher than a height level of an upper surface of the source conductive layer (150),
wherein the first channel semiconductor layer and the second channel semiconductor layer are connected in a connection region [CL] between the first channel structure and the second channel structure.
Lee fails to teach wherein the source conductive layer directly contacts the first channel semiconductor layer and the second channel semiconductor layer in the connection region.
LEE teaches wherein the source conductive layer (185, FIG. 10B, ¶ [0060]) directly contacts the first channel semiconductor layer (lower 167) and the second channel semiconductor layer (upper 167) in the connection region.
It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of minimizing the size of the semiconductor device as taught by LEE, ¶ [0003].
Moreover, Lee fails to teach a first bit line disposed below the first channel structure.
IIJIMA teaches a first bit line (24, FIG. 4, ¶ [0019]) disposed below the first channel structure (CL).
It would have been prima facie obvious to one of ordinary skill in the art at the time the invention was made to include the above said teaching for the purpose of providing the flexibility of manufacturing the memory device by having the bit line forming underneath the channel region as taught by IIJIMA.
Finally, after the combining of Lee and IIJIMA would teach a first bit line;
a second bit line on the first bit line;
a source conductive layer (150, [0053]) between the first bit line and the second bit line;
Re claim 4, in the combination, IIJIMA, FIG. 1 teaches the semiconductor device as claimed in claim [[2]] 1, wherein the first bit line (BL) is configured to apply a first electrical signal to the first channel semiconductor layer (bottom half of 24), and Lee, FIG. 9 the second bit line (BL) is configured to apply a second electrical signal to the second channel (121 of (120a2)) semiconductor layer, independently of the first bit line.
Re claim 5, in the combination, Lee, FIG. 9 teaches the semiconductor device as claimed in claim 1, wherein the source conductive layer (150) spaced apart in the first direction from a lowermost first gate electrode (bottom-most 121 of (120a1)) among the plurality of first gate electrodes and an uppermost second gate electrode (upper-most 121 of (120a2)) among the plurality of second gate electrodes.
Re claim 6, in the combination, IIJIMA, FIG. 23 teaches the semiconductor device as claimed in claim 1, wherein each of the first channel structure (CL in region 64) and the second channel structure (CL in region 61) has an inclined side surface such that each of the first channel structure and the second channel structure has an increased width towards the first bit line (44(BL)).
Re claim 7, in the combination, IIJIMA, FIG. 23 teaches the semiconductor device as claimed in claim 6, wherein an upper surface of the first channel structure (CL in region 64) has a width smaller than a width of a lower surface of the second channel structure (CL in region 61).
Re claim 10, in the combination, Lee, FIG. 9 teaches the semiconductor device as claimed in claim 1,
wherein the first channel structure [CH1] further includes a first gate dielectric (122 of (120a1)) layer between the first channel semiconductor layer and the plurality of first gate electrodes (121 of (120a1), [0037]), and the second channel structure [CH2] further includes a second gate dielectric layer (122 of (120a2)) between the second channel semiconductor layer and the plurality of second gate electrodes (121 of (120a2)), and
wherein the first gate dielectric layer (122 of (120a1)) and the second gate dielectric layer (122 of (120a2)) are spaced apart (vertically) from each other in the first direction between the first channel structure and the second channel structure.
Re claim 12, in the combination, Lee, FIG. 9 teaches the semiconductor device as claimed in claim 1, further comprising a first horizontal conductive layer (121 of (120a1)) and a second horizontal conductive layer (121 of (120a2)) on the upper surface and the lower surface of the source conductive layer (150), respectively.
Claim(s) 3, 8-9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of LEE and further in view of IIJIMA and Zhang (Patent No.: US 9570463).
Re claim 8-9, Lee/LEE/IIJIMA teaches all the limitation of claim 1/10.
Lee/LEE/IIJIMA fails to teach the limitation of claim 3, 8-9/11.
Zhang teaches wherein the source conductive layer (148+42), FIG. 13B) has a contact region protruding from side surfaces of the plurality of first gate electrodes (146) and the plurality of second gate electrodes (246) to an external side, and
wherein the semiconductor device further includes a source contact plug (66, FIG. 14B) connected to the source conductive layer (148+42) in the contact region and configured to apply the electrical signal (claim 3).
wherein the source conductive layer (148+42, FIG. 13B) expands towards the first channel structure [CH1] and the second channel structure [CH2] in the connection region such that the source conductive layer has an increased thickness in the first direction (vertical) (claim 8).
wherein a maximum width (along 42) of a lower surface of the source conductive layer (148+42) facing the first channel structure [CH1] is less than a maximum width of an upper surface of the source conductive layer facing the second channel structure [CH2] (claim 9).
wherein the source conductive layer (148+42) has protruding regions expanding along the first direction towards the first channel structure (along the upper portion of 42) and the second channel structure in the connection region, and wherein the protruding regions directly contact the first gate dielectric layer (132) and the second gate dielectric layer (232) (claim 11).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of providing enhanced control of a portion of a semiconductor channel in the memory stack as taught by Zhang, Abstract.
Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (Patent No.: US 9570463) in view of IIJIMA and further in view of LEE.
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Re claim 13, Zhang, FIG. 13B teaches a semiconductor device, comprising:
a first semiconductor structure (10/11/9) including a substrate and a circuit device (10/11) disposed on the substrate (9); and
a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure,
wherein the second semiconductor structure includes:
a plurality of first gate electrodes (146) stacked in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other;
a first channel structure [CH1] penetrating the plurality of first gate electrodes and including a first channel semiconductor layer;
a plurality of second gate electrodes (246) on the first gate electrodes and stacked in the first direction and spaced apart from each other;
a second channel structure [CH2] penetrating the plurality of second gate electrodes and including a second channel semiconductor layer; and
a source conductive layer between an uppermost first gate electrode among the plurality of first gate electrodes and a lowermost second gate electrode among the plurality of second gate electrodes,
wherein the first channel semiconductor layer extends above the first channel structure and the second channel semiconductor layer extends below the second channel structure such that the first channel semiconductor layer and the second channel semiconductor layer are connected in a connection region (148+42+62) between the first channel structure and the second channel structure,
wherein the source conductive layer (148+42) directly contacts the first channel semiconductor layer and the second channel semiconductor layer in the connection region, and
wherein a maximum width of a lower surface of the source conductive layer (148+42) facing the first channel structure [CH1] is less than a maximum width of an upper surface of the source conductive layer facing the second channel structure [CH2].
Zhang fails to teach a first bit line below the first channel structure.
IIJIMA teaches a first bit line (44, FIG. 23, ¶ [0019]) below the first channel structure (CL of region 64).
It would have been prima facie obvious to one of ordinary skill in the art at the time the invention was made to include the above said teaching for the purpose of providing the flexibility of manufacturing the memory device by having the bit line forming underneath the channel region as taught by IIJIMA.
Moreover, Zhang fails to teach a second bit line on the second channel structure.
LEE teaches a second bit line (195, FIG. 11C, [0134]) on the second channel structure (167, [0060]).
It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of minimizing the size of the semiconductor device as taught by LEE, ¶ [0003].
Re claim 14, in the combination, Zhang, FIG. 13B teaches the semiconductor device as claimed in claim 13, wherein the source conductive layer (148+42+60) includes an internal conductive layer (148+42) and a barrier layer (60) extending along an external surface of the internal conductive layer.
Re claim 15, in the combination, Zhang, FIG. 13B teaches the semiconductor device as claimed in claim 14, wherein the barrier layer (60) directly contacts the first channel semiconductor layer [CH1] and the second channel semiconductor layer [CH2] in the connection region.
Re claim 16, in the combination, Zhang, FIG. 13B teaches the semiconductor device as claimed in claim 13, further comprising:
separation insulating layers (132/232) penetrating the plurality of first gate electrodes (146) and the plurality of second gate electrodes (246), extending in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction,
wherein the source conductive layer (148+42) is a single layer between the separation insulating layers adjacent to each other in the third direction.
Re claim 17, in the combination, Zhang, FIG. 13B teaches the semiconductor device as claimed in claim 13, wherein the source conductive layer has a first region having a first thickness (vertical width of 148) in the first direction, and has a second region having a second thickness (vertical width of 42) in the first direction that is greater than the first thickness.
Re claim 18, in the combination, Zhang, FIG. 13B teaches the semiconductor device as claimed in claim 17, wherein the second region (occupied by 42) is surrounded by the first region (occupied by 148).
Re claim 19, in the combination, Zhang, FIG. 13B teaches the semiconductor device as claimed in claim 13,
wherein the first channel structure and the second channel structure form a first memory cell string (occupied by 142/60/[CH1]) and a second memory cell string (occupied by 242/60/[CH2]), respectively, and
wherein the first memory cell string and the second memory cell string are independently controlled by the first bit line (BL, FIG. 4 of IIJIMA) and the second bit line (195 of FIG. 11C of LEE), respectively.
Re claim 20, in the combination, Zhang, FIG. 13B teaches the semiconductor device as claimed in claim 13,
wherein the source conductive layer (148+42) is configured to apply an electrical signal to the first channel semiconductor layer [CH1] and the second channel semiconductor layer [CH2] as a common source line, and
wherein the first bit line (BL, FIG. 4 of IIJIMA) is configured to apply a first electrical signal to the first channel semiconductor layer [CH1], and the second bit line (195 of FIG. 11C of LEE) is configured to apply a second electrical signal to the second channel semiconductor layer [CH2].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2894
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