DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
3. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 16-20 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
4. Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. As analyzed under the current 2019 Revised Patent Subject Matter Eligibility Guidance; first, the claim is directed to a proper statutory category. Second, under step 2A prong 1, the claim is directed to abstract ideas; specifically mathematical concepts such as mathematical calculations and/or mental processes, can be done by pen and paper. They are highlighted below (underlined, italicized):
16. A computer-implemented method for computing a sum of product values using N arrays of asynchronous accumulators, comprising:
receiving a set of weights and a set of activations, wherein the weights and the activations are represented in logarithmic form;
summing each weight in the set of weights with each activation in the set of activations to compute product values, wherein each product value includes a sign, a quotient component, and a remainder component and each asynchronous accumulator within one of the N arrays corresponds to a different possible value of the remainder component;
either incrementing or decrement according to the sign, by a first asynchronous accumulator within a first one of the N arrays, a single bit of a partial sum output by the first asynchronous accumulator based on a first one of the quotient components;
multiplying the partial sum by the value of the remainder component corresponding to the first asynchronous accumulator to produce a scaled partial sum; and
adding the scaled partial sum to additional scaled partial sums to produce the sum of the product values.
As currently recited, under the broadest reasonable interpretation, these highlighted limitations can be interpreted as mathematical concepts and/or mental processes, or performed by pen and paper.
Next, under step 2A prong 2, are there additional elements or combination of elements that apply or integrate the judicial exception into a practical application? The additional limitation of “N arrays of asynchronous accumulators” is recited at a high-level of generality (i.e., generic machine) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Further the claim recites “receiving...” However, this step is recited as a general means of receiving data for use by the abstract idea, and thus fails to impose a meaningful limit on the remaining steps. Such data receiving operations could be attached to any calculation and is necessary for use of the judicial exception, amounting to mere gathering and/or insignificant extra-solution activity.
Lastly, under step 2B are there limitations indicative of an inventive concept (i.e. significantly more)? No, the additional limitations do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements are no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. See MPEP 2106.05(f). Furthermore, receiving data that is necessary for use of the recited judicial exception represents mere data gathering/data output and is insignificant extra solution activity. The courts have found limitations directed to outputting/storing information electronically, recited at a high level of generality, to be well-understood, routine, and conventional. See MPEPE 2106.05(d)(II). The claim is not patent eligible.
5. Dependent claims 17-20 are rejected under 35 U.S.C. 101 as non- statutory for at least the reason stated above, as they do not add any feature or subject matter that would solve the non-statutory deficiencies of the independent claims from which they depend. The claims depend from claim 1, but fail to include any additional elements sufficient to amount to significantly more than the judicial exception. The claims recite further limitations that abstract mathematical concepts and/or mental steps without reciting any additional limitations that make the claim any less abstract or that impose meaningful limits on practicing the abstract idea. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
6. Claim 17 recites the abstract idea of “wherein the N arrays are configured to compute partial sums of products of N weights and M activations,” and thus similarly rejected as claim 16 above for failing to recite additional limitations that integrate the abstract idea into a practical application and impose meaningful limits on practicing the abstract idea and for failing to include additional elements that are sufficient to amount to significantly more than the judicial exception.
7. Claim 18 recites the abstract idea of “wherein the set of activations includes M activations and a different one of the M activations are input to each one of M vector inference engines and the N weights are broadcast to the N arrays within each one of the vector inference engines,” and thus similarly rejected as claim 16 above for failing to recite additional limitations that integrate the abstract idea into a practical application and impose meaningful limits on practicing the abstract idea and for failing to include additional elements that are sufficient to amount to significantly more than the judicial exception.
8. Claim 19 recites the abstract idea of “wherein an accumulator selection signal is a one-hot encoding of the remainder component and each one of the asynchronous accumulators is associated with a different bit of the accumulator selection signal,” and thus similarly rejected as claim 16 above for failing to recite additional limitations that integrate the abstract idea into a practical application and impose meaningful limits on practicing the abstract idea and for failing to include additional elements that are sufficient to amount to significantly more than the judicial exception.
9. Claim 20 recites the abstract idea of “wherein the asynchronous accumulators comprise asynchronous up/down accumulator cells,” and thus similarly rejected as claim 16 above for failing to recite additional limitations that integrate the abstract idea into a practical application and impose meaningful limits on practicing the abstract idea and for failing to include additional elements that are sufficient to amount to significantly more than the judicial exception.
Allowable Subject Matter
10. Claims 1-15 allowed.
Claims 16-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The claims recite at least a vector adder configured to compute product values by summing each weight in a set of weights with each activation in a set of activations, wherein the weights and the activations are represented in logarithmic form, each product value including a quotient component and a remainder component; N arrays of asynchronous accumulators, wherein, within each one of the N arrays: each asynchronous accumulator corresponds to a different possible value of the remainder component and is configured to increment or decrement a single bit of a partial sum based on the quotient component; and a scale unit coupled to each asynchronous accumulator multiplies the partial sum by the value of the remainder component corresponding to the asynchronous accumulator to produce a scaled partial sum; and an addition unit adds the scaled partial sums to produce a sum of the product values.
The closest prior art of record US Pat. 9,496,917 is related to accumulation apparatus, which adds a number of data values, has an adder and an asynchronous ripple counter. The adder adds each current data value to an adder sum of the preceding data values. The asynchronous ripple counter, which is coupled to the adder, generates a ripple count by counting occurrences of overflow of the adder. The accumulation apparatus outputs an accumulated data value having the adder sum as least significant part and the ripple count as most significant part.
However, the prior art of record does not teach or suggest at least a vector adder configured to compute product values by summing each weight in a set of weights with each activation in a set of activations, wherein the weights and the activations are represented in logarithmic form, each product value including a quotient component and a remainder component; N arrays of asynchronous accumulators, wherein, within each one of the N arrays: each asynchronous accumulator corresponds to a different possible value of the remainder component and is configured to increment or decrement a single bit of a partial sum based on the quotient component; and a scale unit coupled to each asynchronous accumulator multiplies the partial sum by the value of the remainder component corresponding to the asynchronous accumulator to produce a scaled partial sum; and an addition unit adds the scaled partial sums to produce a sum of the product values.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 2020/0310758 -related to a Multiply Accumulate (MAC) hardware accelerator, which may be used, for example, in deep convolutional neural networks (DCNN).
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151