DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Claims 10, 12, and 14-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species and subspecies, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 08/04/2026.
Applicant's election with traverse of Species I (Fig 3), subspecies B (Fig 8) in the reply filed on 08/04/2026 is acknowledged. Subspecies B does not appear to draw to claims other than the generic claims. Claims 1-6, 8-9, 23, 27 are still pending.
The traversal is on the ground(s) that first, the Office Action mailed on 06/23/2026 did not identify the claims associated with each of the subspecies. Applicant is citing MPEP § 814(II) to support his traverse.
This is not found persuasive because MPEP § 814(II) does apply to Inventions other than species, so not for the current species restriction.
MPEP § 809.02(a) states that:
Action as follows should be taken:
(A) Identify generic claims or indicate that no generic claims are present. See MPEP § 806.04(d) for definition of a generic claim.
(B) Clearly identify each (or in aggravated cases at least exemplary ones) of the disclosed species, to which claims are to be restricted. The species are preferably identified as the species of figures 1, 2, and 3 or the species of examples I, II, and III, respectively. In the absence of distinct figures or examples to identify the several species, the mechanical means, the particular material, or other distinguishing characteristic of the species should be stated for each species identified. If the species cannot be conveniently identified, the claims may be grouped in accordance with the species to which they are restricted. Provide reasons why the species are independent or distinct.
(C) Applicant should then be required to elect a single disclosed species under 35 U.S.C. 121, and advised as to the requisites of a complete reply and their rights under 37 CFR 1.141.
Species and subspecies are identified as the species of figures (see Office Action mailed on 6/23/2026 and repeated below for clarification ), so the species and subspecies are clearly identified.
Here is how the restriction paragraph on species and subspecies was intended:
This application contains claims directed to the following patentably distinct species (Presence or not of a first dielectric material layer 224A):
Species I directed to Figure 3 with the backside 220 of the semiconductor device 204 comprising a dielectric material layer, e.g., a first dielectric material layer 224A and a second dielectric material layer 224B ([0067]), appears to be drawn to claims 10, 12, 14-15, 16-18, 19-21.
Species II directed to Figure 5 with a dielectric structure having a variation of cross-like shape([0071]; does not appear to be drawn to any claim.
The Species are independent or distinct because:
The listed Species offer the choice between two different combination with a first dielectric material layer 224A (Fig 3), or without a first dielectric material layer 224A (Fig 5).
Subsequent to an election of a species, Applicant is advised to elect a respective subspecies to said elected species (Variation of arrangements of dielectric material layers 224A):
Subspecies A directed to Figure 3 with the cold plate 206 attached to the semiconductor device 204 using a hybrid bonding technique, where bonds are formed between the dielectric material layers 224A, 224B and between metal features, such as between first metal pads and second metal pads, disposed in the dielectric material layers 224A, 224B ([0071]).
Subspecies B directed to Figure 8 with a semiconductor device 804 bonded to the cold plate 306 using a multifunctional layer 824 ([0109]).
Subspecies C directed to Figure 9 with the semiconductor device 904 bonded to the cold plate 906 using at least a multifunctional layer 924 and a dielectric layer 926 ([0116]), appears to be drawn to claims 10, 12, 14-15, 19-21.
Subspecies D directed to Figure 10 with the semiconductor device 1004 bonded to the cold plate 1006 using at least a multifunctional layer 1024 and a dielectric layer 1026. That is, the dielectric layer 1026 and the multifunctional layer 1024 are disposed between the cold plate 1006 and a semiconductor device 1004 ([120]), appears to be drawn to claims 10, 12, 14-15, 16-18.
Subspecies E directed to Figure 11, with the semiconductor device 1004 bonded to the cold plate 1006 using at least a multifunctional layer 1024 and a dielectric layer 1026. That is, the dielectric layer 1026 and the multifunctional layer 1024 are disposed between the cold plate 1006 and a semiconductor device 1004 ([120]), appears to be drawn to claims 10, 12, 14-15, 19-21.
Subspecies F directed to Figure 11, with a multifunctional layer 1124 and a dielectric layer 1126 disposed between the semiconductor device 1104 and the cold plate 1106 with a thermal oxide layer 1100 on (all) external surfaces of the cold plate 1106 instead of the dielectric layer 1126 ([0125]), appears to be drawn to claims 10, 12, 14-15.
The subspecies are independent or distinct because:
The listed Subspecies offer the choice between six different of arrangements of dielectric material layers 224A as presented above.
Second, the traversal is also on the ground(s) that the Office Action mailed on 06/23/2026 identified the claims 1-6, 8-10, 13, 18-20 as generic. Applicant traversed the list having claim 13. This is found persuasive because claim 13 (canceled) was listed instead of claim 12 due to a typographical error.
While the traversal is also on the ground of having an explanation of why the claims appear generic, this is not found persuasive because there is no requirement to explain why they are generic (see MPEP § 809.02(a) stated above).
Here is how the restriction paragraph on generic claims was intended:
Applicant is required under 35 U.S.C. 121 to elect a single disclosed species, or a single grouping of patentably indistinct species, for prosecution on the merits to which the claims shall be restricted if no generic claim is finally held to be allowable. Currently claims 1-6, 8-9, 23, and 27 appear generic.
Finally, the traversal is on the ground(s) that the Office Action mailed on 06/23/2026 identified claim 12 as generic to subspecies B, C, D, E, and F. This is not found persuasive because claim 12 has an additional dielectric layer which is absent in Fig 8 associated with subspecies B. Consequently, claim 12 is not a feature of subspecies B, so claim 12 cannot be generic to all species and subspecies.
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim 23 is objected to because of the following informalities:
Claim 23 recites “an SixOyNz nitride” in Line L2 but should read –a SixOyNz nitride --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 27, the term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as " to a great extent or degree”” (see thefreedisctionnary.com). This language is indefinite as the specification does not describe what substantially means in regard of sidewalls extending in parallel. Would this mean that the sidewalls can cross further away or should only extend in parallel? Thus, it is unclear because defining how sidewalls are extending in parallel or not is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, each claim and all claims depending therefrom is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Under the principles of compact prosecution, the claim “sidewalls extending substantially in parallel” limitation is being interpretated as – sidewalls extending in parallel--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-9, 23 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Haba et al. (US20240038633A1 from IDS-Haba33).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Haba33 discloses an integrated cooling assembly comprising:
a semiconductor device (Semiconductor device 304-Examiner's annotated Fig 4) and
a cold plate attached to the semiconductor device by direct bonds with a multifunctional layer disposed therebetween (Cold plate 324/326 attached to semiconductor device 304 by direct bond with a multifunctional layer 430/432 comprising nitride- [0045] L9-11, [0045] L12-24-Examiner's annotated Fig 4),
the cold plate comprising:
a perimeter sidewall (Cold plate 324/326 comprising perimeter sidewall 424 Top Layer, perimeter sidewall extending downwardly from top portion 326 to backside of semiconductor device 304 as indicated by the dashed line rectangle-Examiner's annotated Fig 4);
a top portion (Cold plate 324/326 comprising Top portion 326-Examiner's annotated Fig 4); and
a cavity divider comprising cavity sidewalls (Cold plate 324/326 comprising cavity divider 312/408 comprising cavity sidewalls, extending downwardly from top portion 326 to a backside of semiconductor 304, as indicated by vertical lines-Examiner's annotated Fig 4), wherein:
the perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate (Cold plate 324/326 comprising perimeter sidewall 424 Top Layer, the perimeter sidewall extending downwardly from top portion 326 to backside of semiconductor device 304 defining a perimeter of the cold plate 324/326 as indicated by the dashed line rectangle-Examiner's annotated Fig 4);
the cavity divider extends downwardly from the top portion towards the backside of the semiconductor device (Cold plate 324/326 comprising cavity divider 312/408 comprising cavity sidewalls, extending downwardly from top portion 326 to a backside of semiconductor 304, as indicated by vertical lines-Examiner's annotated Fig 4);
the cavity sidewalls, the perimeter sidewall and the backside of the semiconductor device collectively define coolant channels therebetween (Cavity sidewalls, perimeter sidewall and backside of semiconductor device 304 collectively defining coolant channels 310/ channels between 408 therebetween, as indicated by continuous lines-Examiner's annotated Fig 4); and
the multifunctional layer comprises a nitride (multifunctional layer 430/432 comprising nitride-[0045] L12-24).
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Regarding claim 2, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly:
wherein a thickness of the multifunctional layer in a direction orthogonal to the backside of the semiconductor device is less than or equal to 1_μm (multifunctional layer 430/432 deposed on semiconductor device 304 so having a thickness in a direction orthogonal to the backside of the semiconductor device 304 being equal or less than 500nm so less than or equal to 1_μm-[0046] L 1-7).
Regarding claim 3, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly :
wherein a thickness of the multifunctional layer in a direction orthogonal to the backside of the semiconductor device is less than or equal to 50_nm (multifunctional layer 430/432 deposed on semiconductor device 304 so having a thickness in a direction orthogonal to the backside of the semiconductor device 304 being equal or less than 100 nm so being less than 50nm-[0046] L 1-7).
Regarding claim 4, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly :
wherein a thickness of the multifunctional layer in a direction orthogonal to the backside of the semiconductor device is 20_nm to 1_μm (multifunctional layer 430/432 deposed on semiconductor device 304 so having a thickness in a direction orthogonal to the backside of the semiconductor device 304 being equal or less than 500nm and being 50 nm or more so being 20_nm to 1_μm-[0046] L 1-7).
Regarding claim 5, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly
wherein a thickness of the multifunctional layer in a direction orthogonal to the backside of the semiconductor device is 20_nm to 50nm (multifunctional layer 430/432 deposed on semiconductor device 304 so having a thickness in a direction orthogonal to the backside of the semiconductor device 304 being equal or less than 100 nm and being 10 nm or more so being 20_nm to 50_nm-[0046] L 1-7).
Regarding claim 6, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly
wherein a thickness of the multifunctional layer in a direction orthogonal to the backside of the semiconductor device is 20_nm to 40nm (multifunctional layer 430/432 deposed on semiconductor device 304 so having a thickness in a direction orthogonal to the backside of the semiconductor device 304 being equal or less than 100 nm and being 10 nm or more so being 20_nm to 40_nm-[0046] L 1-7).
Regarding claim 8, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly
wherein the cold plate is attached to the semiconductor device using direct dielectric bonds formed between the multifunctional layer and the cold plate (Cold plate 324/326 attached to semiconductor device 304 by direct dielectric bond with a multifunctional layer 430/432 comprising nitride- [0045] L9-11, [0045] L12-24, [0046] L7-12-Examiner's annotated Fig 4).
Regarding claim 9, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly
wherein the cold plate is attached to the semiconductor device using direct hybrid bonds formed between the multifunctional layer and the cold plate (Cold plate 324/326 attached to semiconductor device 304 by direct hybrid bond with a multifunctional layer 430/432 comprising nitride- [0045] L9-11, [0045] L12-24, [0047] L1-9-Examiner's annotated Fig 4).
Regarding claim 23, Haba33 discloses all the elements of claim 1, as noted above.
Haba33 further discloses an integrated cooling assembly
wherein the multifunctional layer comprises a SixOyNz nitride (multifunctional layer 430/432 comprising silicon oxynitride so SixOyNz nitride-[0045] L12-24)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. (US20220037231A1 from IDS-Hsiao31) in view of Elsherbini et al. (US 20210407888 A1-Elsherbini88).
`Regarding claim 1, Hsiao31 discloses an integrated cooling assembly (Abstract) comprising:
a semiconductor device (Semiconductor device 118-Examiner's annotated Fig 13B) and
a cold plate attached to the semiconductor device by direct bonds with a multifunctional layer disposed therebetween (Cold plate 140/168 attached to semiconductor device 118 by dielectric-to-dielectric so direct bond with a multifunctional layer bottom 140 as by the dot line rectangle -[0033] L1-33-Examiner's annotated Fig 13B),
the cold plate comprising:
a perimeter sidewall (Cold plate 140/168 comprising perimeter sidewall 140 Top Layer, the perimeter sidewall extending downwardly from top portion 168 to backside of semiconductor device 118 defining a perimeter of the cold plate 140/168 as indicated by the dashed line rectangle-Examiner's annotated Fig 13B);
a top portion (Cold plate 140/168 comprising Top portion 168 -Examiner's annotated Fig 13B); and
a cavity divider comprising cavity sidewalls (Cold plate 140/168 comprising cavity divider 142 comprising cavity sidewalls 142 sidewalls, extending downwardly from top portion 168 to a backside of semiconductor 118, as indicated by vertical lines-Examiner's annotated Fig 13B), wherein:
the perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate (perimeter sidewall 140 Top Layer, the perimeter sidewall extending downwardly from top portion 168 to backside of semiconductor device 118 defining a perimeter of the cold plate 140/168 as indicated by the dashed line rectangle-Examiner's annotated Fig 13B);
the cavity divider extends downwardly from the top portion towards the backside of the semiconductor device (cavity divider 142 extending downwardly from top portion 168 to a backside of semiconductor 118, as indicated by vertical lines-Examiner's annotated Fig 13B);
the cavity sidewalls, the perimeter sidewall and the backside of the semiconductor device collectively define coolant channels therebetween (Cavity sidewalls 142, perimeter sidewall 140 Top layer and backside of semiconductor device 118 collectively defining coolant channels 142 therebetween-Examiner's annotated Fig 13B).
Hsiao31 does not disclose an integrated cooling assembly wherein
the multifunctional layer comprises a nitride.
Elsherbini88 teaches an integrated cooling assembly wherein
the multifunctional layer comprises a nitride (multifunctional layer /101 bottom layer comprising nitride ([0050] L 1-19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated cooling assembly of Fountain16 as taught by Elsherbini88 for the purpose of tailoring thermal solution for specific IC device and increasing efficiency (Elsherbini88:[0035]).
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Regarding claim 27, Hsiao31 and Elshernini88 combination discloses all the elements of claim 1, as noted above.
Hsiao31 further discloses an integrated cooling assembly wherein the cold plate comprises
adjacent first and second cavity dividers each comprising cavity sidewalls extending substantially in parallel (Adjacent first and second cavity dividers 142D having sidewalls extending in parallel as indicated by dashed lines-Examiner's annotated Fig 9G);
the cavity sidewalls are sloped and form an acute angle with the backside of the semiconductor device (Adjacent first and second cavity dividers 142D having sloped sidewalls forming an angle less than 90 degree so acute angle with the backside of semiconductor device 118 as indicated by dashed lines-Examiner's annotated Fig 9G, Fig 13B); and
opposing cavity sidewalls of the adjacent first and second cavity dividers and the backside of the semiconductor device define a triangular cross-section of a corresponding coolant channel to define plural coolant channels (Adjacent first and second cavity dividers 142D opposing sidewalls and backside of semiconductor device 118 defining a triangular cross-section of corresponding coolant channel 142D defining plural coolant channel 142D as indicated by dot and dashed lines-[0037] L19-24).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fountain, JR et al. (US 20260198316 A1-Fountain16) discloses an integrated cooling assembly comprising: a semiconductor device and a cold plate attached to the semiconductor device by direct bonds with a multifunctional layer disposed therebetween, the cold plate comprising: a perimeter sidewall; a top portion; and a cavity divider comprising cavity sidewalls, wherein: the perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate; the cavity divider extends downwardly from the top portion towards the backside of the semiconductor device; the cavity sidewalls, the perimeter sidewall and the backside of the semiconductor device collectively define coolant channels therebetween; and the multifunctional layer comprises a nitride (Fig 3, Fig 8, Abstract).
Park et al. (US 20230298969 A1 from IDS-Park69) discloses an integrated cooling assembly comprising: a semiconductor device and a cold plate attached to the semiconductor device by direct bonds with a multifunctional layer disposed therebetween (Fig 1A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/22/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
