DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
On 09/30/2025, a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s response filed 09/13/2025 has been entered.
Summary of Response
3. The 09/13/2025 response includes: (a) claims 1 and 20-21 are currently amended; (b) claims 8-9 are previously presented; (c) claims 3-7 and 10-19 are original; (d) claim 2 is canceled; and (e) the grounds for rejection set forth in the 07/24/2025 office action are traversed. Claims 1 and 3-21 are currently pending and an office action follows:
Response to Arguments
4. Applicant's arguments filed 09/13/2025 with respect to the rejections of claims 1, 3-11 and 13-21 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection of claims 1, 3-11 and 13-21 is made in view a new interpretation of the previously-cited prior art, in which Kim’s Vss (FIGs. 4-5, ¶0060, especially – “second power supply line Vss”) is cited as a first power supply voltage line. A new objection to claim 20 is set forth below. Finally claim 12 remains allowable, if rewritten in independent form as explained below.
Claim Objection
5. Claim 20 is objected to because of the following informalities:
Claim 20 at line 15 includes an extra space between “electrode,” and “and”. This objection may be overcome, for example, removing this extra space”. Appropriate correction is required.
Claim Rejections – 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1, 3-4, 7-9, 14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2007/0040770 A1 to Kim in view of U.S. Patent Pub. No. 2016/0291368 A1 to Kim et al. (“Kim II”) in view of Korea Patent Pub. No. 20070035860 A to Jeong et al. (“Jeong”).
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As to claim 1, Kim discloses a display panel(100)(FIG. 2; ¶0041) of a display device (FIG. 2; ¶¶0013, 0041), the display panel(100)(FIG. 2; ¶0041) comprising:
a first pixel(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit first color light(red)(FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081, 0088);
a second pixel(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit second color light(green)(FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081, 0088); and
a third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit third color light(blue)(FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081, 0088),
wherein each of the first(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081), second(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) and third pixels(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) includes:
a first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) including a first electrode(Cst’s top electrode)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to a first power supply voltage line(Vss)(FIGs. 4-5; ¶0060), and a second electrode(Cst’s bottom electrode)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to a gate node(node N connecting M1’s gate terminal with Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0063);
a first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) including a gate electrode(M1’s gate terminal)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to the gate node(N)(FIGs. 4-5: 111R, 111G, 111B, M1; ¶0063);
a second transistor(M2)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) configured to transfer a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) to a source(M1’s terminal directly connected to M2)(FIGs. 4-5: 111R, 111G, 111B; ¶0063) of the first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0063) in response to a gate writing signal(Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0062) of a gate writing signal line (line directly connected to Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0062);
a third transistor(M3)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) configured to diode-connect the first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) in response to a gate compensation signal(scan signal Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0064) of a gate compensation signal line(horizontal line directly connected to M3 to provide scan signal Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0064); and
a light emitting element(OLED)(FIGs. 4-5: 111R, 111G, 111B; ¶0059) including an anode(OLED’s top electrode)(FIGs. 4-5; ¶0060), and a cathode(OLED’s bottom electrode)(FIGs. 4-5; ¶0060) coupled to a second power supply voltage line(Vdd)(FIGs. 4-5: 111R, 111G, 111B; ¶0059), and wherein a size of the first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) included in the third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) is determined such that a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081); a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the first pixel(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) or the second pixel(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081).
Kim does not expressly disclose a first capacitor including a first electrode coupled to a first power supply voltage line with no switching element disposed between the first power supply voltage line and the first electrode; and wherein a ratio of a channel width to a channel length of the first transistor in the third pixel is greater than a ratio of a channel width to a channel length of the first transistor in the first pixel or the second pixel, and wherein a size of the first capacitor included in the third pixel is determined such that a data voltage range for the third pixel is adjusted close to a data voltage range for the first pixel or the second pixel.
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Kim II discloses and wherein a ratio of a channel width(horizontal width of CHN3)(FIG. 4B; ¶0082) to a channel length(vertical length of CHN3)(FIG. 4B; ¶0082) of the first transistor(TR31)(FIG. 4B; ¶0082) in the third pixel(PX3)(FIGs. 1-2, 4B; ¶¶0040, 0048, 0082) is greater than a ratio of a channel width(horizontal width of CHN1)(FIG. 4A; ¶0082) to a channel length(vertical length of CHN1)(FIG. 4A; ¶0082) of the first transistor(TR1)(FIG. 4A; ¶0082) in the first pixel(PX1)(FIGs. 2-3; ¶0083) or the second pixel(PX2)(FIGs. 2-3; ¶0083).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim with Kim II to provide a display panel that is able to display images with a desired color coordinate and an improved quality (see e.g., ¶¶0006, 0082, 0084, 0087).
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Jeong discloses and wherein a size of the first capacitor(Cp)(FIG. 9; p 13, ¶2) included in the third pixel(blue pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is determined such that a data voltage range for the third pixel(blue pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is adjusted close to a data voltage range for the first pixel(red pixel)(FIG. 9; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel(green pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim and Kim II with Jeong (i.e., to modify the teachings of Kim and Kim II by adding a parasitic capacitor Cp to each of the first, second and third pixels) to provide a display panel that may be driven more efficiently with an improved image quality (p 14, ¶2). Below is Kim’s FIG. 5 edited to show the teachings of Jeong.
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Kim, Kim II and Jeong teach a display panel (Kim: FIG. 2: 100; ¶0041) of a display device (Kim: FIG. 2; ¶¶0013, 0041), the display panel (Kim: FIG. 2: 100; ¶0041) comprising:
a first pixel configured to emit first color light (Kim: FIGs. 2, 4-5: 111R, red; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2);
a second pixel configured to emit second color light (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2); and
a third pixel configured to emit third color light (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2),
wherein each of the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) includes:
a first capacitor (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP; p 13, ¶2) including a first electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s bottom electrode; p 13, ¶2) coupled to a first power supply voltage line (Kim: FIGs. 4-5: Vss, 111R, 111G, 111B; ¶0060) with no switching element disposed between the first power supply voltage line (Kim: FIGs. 4-5: Vss, 111R, 111G, 111B; ¶0060) and the first electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s bottom electrode; p 13, ¶2), and a second electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s top electrode; p 13, ¶2) coupled to a gate node (Kim: FIGs. 4-5: node N connecting M1’s gate terminal with Cst, 111R, 111G, 111B; ¶0063);
a first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) including a gate electrode (Kim: FIGs. 4-5: M1’s gate terminal, 111R, 111G, 111B; ¶0061) coupled to the gate node (Kim: FIGs. 4-5: N, 111R, 111G, 111B, M1; ¶0063);
a second transistor (Kim: FIGs. 4-5: M2, 111R, 111G, 111B; ¶0061) configured to transfer a data voltage (Kim: FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) to a source (Kim: FIGs. 4-5: M1’s terminal directly connected to M2, 111R, 111G, 111B; ¶0063) of the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in response to a gate writing signal (Kim: FIGs. 4-5: Sn, 111R, 111G, 111B; ¶0062) of a gate writing signal line (Kim: FIGs. 4-5: line directly connected to Sn, 111R, 111G, 111B; ¶0062);
a third transistor (Kim: FIGs. 4-5: M3, 111R, 111G, 111B; ¶0061) configured to diode-connect the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in response to a gate compensation signal (Kim: FIGs. 4-5: scan signal Sn, 111R, 111G, 111B; ¶0064) of a gate compensation signal line (Kim: FIGs. 4-5: horizontal line directly connected to M3 to provide scan signal Sn, 111R, 111G, 111B; ¶0064); and
a light emitting element (Kim: FIGs. 4-5: OLED, 111R, 111G, 111B; ¶0059) including an anode (Kim: FIGs. 4-5: OLED’s top electrode; ¶0060), and a cathode (Kim: FIGs. 4-5: OLED’s bottom electrode; ¶0060) coupled to a second power supply voltage line (Kim: FIGs. 4-5: Vdd; ¶0059), and wherein a ratio of a channel width (Kim II: FIG. 4B: horizontal width of CHN3; ¶0082) to a channel length (Kim II: FIG. 4B: vertical length of CHN3; ¶0082) of the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in the third pixel (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is greater than a ratio of a channel width (Jeong: FIG. 4A: horizontal width of CHN1; ¶0082) to a channel length (Jeong: FIG. 4A: vertical length of CHN1; ¶0082) of the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in the first pixel (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), and wherein a size of the first capacitor (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP; p 13, ¶2) included in the third pixel (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is determined such that a data voltage range (Jeong: FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the third pixel (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is adjusted close to a data voltage range for the first pixel (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
As to claim 3, Kim, Kim II and Jeong teach the display panel of claim 1, as applied above.
Kim, Kim II and Jeong further teach wherein each of the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) further includes:
a second capacitor(Kim: FIGs. 4-5: Caux, 111R, 111G, 111B; ¶0076) including a first electrode(Kim: FIGs. 4-5: Caux’s electrode closest to M1, 111R, 111G, 111B; ¶0075) coupled to the gate node (Kim: FIGs. 4-5: node N connecting M1’s gate terminal with Cst, 111R, 111G, 111B; ¶0063), and a second electrode(Kim: FIGs. 4-5: Caux’s electrode furthest from M1, 111R, 111G, 111B; ¶0075) coupled to the gate writing signal line (Kim: FIGs. 4-5: Sn, 111R, 111G, 111B; ¶0059).
The motivation to combine the additional teachings of Kim II and Jeong is for the same reasonings set forth above for claim 1.
As to claim 4, Kim, Kim II and Jeong teach the display panel of claim 1, as applied above.
Kim II further discloses wherein the channel width(horizontal width of CHN3)(FIG. 4B; ¶0082) of the first transistor(TR32)(FIG. 4B; ¶0082) in the third pixel(PX3)(FIGs. 1-2, 4B; ¶¶0040, 0048, 0082) is greater than the channel width(horizontal width of CHN1)(FIG. 4A; ¶0082) of the first transistor(TR1)(FIG. 4A; ¶0082) in the first pixel(PX1)(FIGs. 2-3; ¶0083) or the second pixel(PX2)(FIGs. 2-3; ¶0083).
The motivation to combine Kim II’s further teachings is the same as the reasoning set forth above for claim 1.
As to claim 7, Kim, Kim II and Jeong teach the display panel of claim 1, as applied above.
Kim, Kim II and Jeong further teach wherein the first capacitor (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP; p 13, ¶2) included in the third pixel (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶¶5-6; p 13, ¶¶6-7; p 14, ¶2) has a size different from a size of the first capacitor (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP; p 13, ¶2) included in the first pixel (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶¶5-6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶¶5-6; p 13, ¶¶6-7; p 14, ¶2).
The motivation to combine the additional teachings of Kim II and Jeong is for the same reasonings set forth above for claim 1.
As to claim 8, Kim, Kim II and Jeong teach the display panel of claim 1, as applied above.
Kim, Kim II and Jeong further teach wherein the size of the first capacitor(Jeong: FIG. 9: Cp; p 13, ¶2) included in the third pixel (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is determined such that the data voltage range for the third pixel (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is adjusted to be disposed between a maximum data voltage of the first pixel (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and the second pixel (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), and a minimum data voltage of the first pixel (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and the second pixel (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
The motivation to combine the additional teachings of Kim II and Jeong is for the same reasonings set forth above for claim 1.
As to claim 9, Kim, Kim II and Jeong teach the display panel of claim 1, as applied above.
Kim, Kim II and Jeong further teach wherein a second capacitor (Kim: FIGs. 4-5: Caux; ¶0076) included in the third pixel (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) has a capacitance lower than a capacitance (Kim: ¶¶0093, 0100) of a second capacitor (Kim: FIGs. 4-5: Caux; ¶0076) included in the first pixel (Kim: FIGs. 2, 4-5: 111R, red; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
As to claim 14, Kim, Kim II and Jeong teach the display panel of claim 1, as applied above.
Kim further discloses the first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) included in the third pixel(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) has a capacitance(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061); a capacitance(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) of the first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) included in the first pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) or the second pixel (111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081).
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Jeong further discloses wherein the first capacitor(Cp)(FIG. 9; p 13, ¶2) included in the third pixel(red pixel)(FIG. 9; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) has a capacitance higher than a capacitance of the first capacitor included in the first pixel(blue pixel)(FIG. 9; p 5, ¶8; p 10, ¶¶3, 5-6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel(green pixel)(FIG. 9; p 5, ¶8; p 10, ¶¶3, 5-6; p 13, ¶¶6-7; p 14, ¶2).
The motivation to combine the additional teachings of Jeong is for the same reasoning set forth above for claim 1.
As to claim 19, Kim, Kim II and Jeong teach the display panel of claim 1, as applied above.
Kim, Kim II and Jeong further teach wherein the first pixel is a red pixel that emits red light (Kim: FIGs. 2, 4-5: 111R, red; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), the second pixel is a green pixel that emits green light (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), and the third pixel is a blue pixel that emits blue light (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
The motivation to combine the additional teachings of Kim II and Jeong is for the same reasonings set forth above for claim 1.
As to claim 20, Kim discloses a display device (FIG. 2; ¶¶0013, 0041) comprising:
a display panel(100)(FIG. 2; ¶0041) including a first pixel(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit first color light(red)(FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081, 0088), a second pixel(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit second color light(green)(FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081, 0088), and a third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit third color light(blue)(FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081, 0088);
a data driver(130, 150)(FIG. 2; ¶¶0048, 0050) configured to provide data voltages (FIG. 1: 30; ¶¶0043, 0045, 0086) to the first(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081), second(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) and third pixels(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081);
a scan driver(120)(FIG. 2: S1 to Sn; ¶0047) configured to provide a gate writing signal(Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0059), a gate compensation signal(scan signal Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0064) and a gate initialization signal(scan signal Sn-1)(FIGs. 4-5; ¶0065) to the first(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081), second(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) and third pixels(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081);
an emission driver(120)(FIG. 2: E1 to En; ¶0047) configured to provide an emission signal (FIG. 2: 120, E1 to En; ¶0047) to the first(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081), second(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) and third pixels(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081); and
a controller(140 or 140 &160)(FIG. 2; ¶¶0048-0051) configured to control the data driver(130, 150)(FIG. 2; ¶¶0048, 0050), the scan driver(120)(FIG. 2: S1 to Sn; ¶0047) and the emission driver(120)(FIG. 2: E1 to En; ¶0047),
wherein each of the first(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081), second(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) and third pixels(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) includes:
a first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) including a first electrode(Cst’s top electrode)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to a first power supply voltage line(Vss)(FIGs. 4-5; ¶0060), and a second electrode(Cst’s bottom electrode)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to a gate node(node N connecting M1’s gate terminal with Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0063);
a first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) including a gate electrode(M1’s gate terminal)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to the gate node(N)(FIGs. 4-5: 111R, 111G, 111B, M1; ¶0063);
a second transistor(M2)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) configured to transfer a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) to a source(M1’s terminal directly connected to M2)(FIGs. 4-5: 111R, 111G, 111B; ¶0063) of the first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0063) in response to a gate writing signal(Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0062) of a gate writing signal line(line directly connected to Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0062);
a third transistor(M3)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) configured to diode-connect the first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) in response to a gate compensation signal(scan signal Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0064) of a gate compensation signal line(horizontal line directly connected to M3 to provide scan signal Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0064); and
a light emitting element(OLED)(FIGs. 4-5: 111R, 111G, 111B; ¶0059) including an anode(OLED’s top electrode)(FIGs. 4-5; ¶0060), and a cathode(OLED’s bottom electrode)(FIGs. 4-5; ¶0060) coupled to a second power supply voltage line(Vdd)(FIGs. 4-5; ¶0059), and wherein a size of the first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) included in the third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) is determined such that a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081); a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the first pixel(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) or the second pixel(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081).
Kim does not expressly disclose a first capacitor including a first electrode coupled to a first power supply voltage line with no switching element disposed between the first power supply voltage line and the first electrode; and wherein a ratio of a channel width to a channel length of the first transistor in the third pixel is greater than a ratio of a channel width to a channel length of the first transistor in the first pixel or the second pixel, and wherein a size of the first capacitor included in the third pixel is determined such that a data voltage range for the third pixel is adjusted close to a data voltage range for the first pixel or the second pixel.
Kim II discloses and wherein a ratio of a channel width(horizontal width of CHN3)(FIG. 4B; ¶0082) to a channel length(vertical length of CHN3)(FIG. 4B; ¶0082) of the first transistor(TR33)(FIG. 4B; ¶0082) in the third pixel(PX3)(FIGs. 1-2, 4B; ¶¶0040, 0048, 0082) is greater than a ratio of a channel width(horizontal width of CHN1)(FIG. 4A; ¶0082) to a channel length(vertical length of CHN1)(FIG. 4A; ¶0082) of the first transistor(TR1)(FIG. 4A; ¶0082) in the first pixel(PX1)(FIGs. 2-3; ¶0083) or the second pixel(PX1)(FIGs. 2-3; ¶0083).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim with Kim II to provide a display device that is able to display images with a desired color coordinate and an improved quality (see e.g., ¶¶0006, 0082, 0084, 0087).
Jeong discloses and wherein a size of the first capacitor(Cp)(FIG. 9; p 13, ¶2) included in the third pixel(blue pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is determined such that a data voltage range for the third pixel(blue pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is adjusted close to a data voltage range for the first pixel(red pixel)(FIG. 9; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel(green pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim and Kim II with Jeong (i.e., to modify the teachings of Kim and Kim II by adding a parasitic capacitor Cp to each of the first, second and third pixels) to provide a display device that may be driven more efficiently with an improved image quality (p 14, ¶2). Below is Kim’s FIG. 5 edited to show the teachings of Jeong.
Kim, Kim II and Jeong teach a display device (Kim: FIG. 2; ¶¶0013, 0041) comprising:
a display panel (Kim: FIG. 2: 100; ¶0041) including a first pixel configured to emit first color light (Kim: FIGs. 2, 4-5: 111R, red; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), a second pixel configured to emit second color light (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), and a third pixel configured to emit third color light (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2);
a data driver (Kim: FIG. 2: 130, 150; ¶¶0048, 0050) configured to provide data voltages (Kim: FIG. 1: 30; ¶¶0043, 0045, 0086) to the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2);
a scan driver (Kim: FIG. 2: 120, S1 to Sn; ¶0047) configured to provide a gate writing signal (Kim: FIGs. 4-5: Sn, 111R, 111G, 111B; ¶0059), a gate compensation signal (Kim: FIGs. 4-5: scan signal Sn, 111R, 111G, 111B; ¶0064) and a gate initialization signal (Kim: FIGs. 4-5: scan signal Sn-1; ¶0065) to the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2);
an emission driver (Kim: FIG. 2: 120, E1 to En; ¶0047) configured to provide an emission signal (Kim: FIG. 2: 120, E1 to En; ¶0047) to the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2); and
a controller (Kim: FIG. 2: 140 or 140 &160; ¶¶0048-0051) configured to control the data driver(Kim: FIG. 2: 130, 150; ¶¶0048, 0050), the scan driver(Kim: FIG. 2: 120, S1 to Sn; ¶0047) and the emission driver (Kim: FIG. 2: 120, E1 to En; ¶0047),
wherein each of the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) includes:
a first capacitor (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP; p 13, ¶2) including a first electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s bottom electrode; p 13, ¶2) coupled to a first power supply voltage line (Kim: FIGs. 4-5: Vss, 111R, 111G, 111B; ¶0060) with no switching element disposed between the first power supply voltage line (Kim: FIGs. 4-5: Vss, 111R, 111G, 111B; ¶0060) and the first electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s bottom electrode; p 13, ¶2), and a second electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s top electrode; p 13, ¶2) coupled to a gate node (Kim: FIGs. 4-5: node N connecting M1’s gate terminal with Cst, 111R, 111G, 111B; ¶0063);
a first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) including a gate electrode (Kim: FIGs. 4-5: M1’s gate terminal, 111R, 111G, 111B; ¶0061) coupled to the gate node (Kim: FIGs. 4-5: N, 111R, 111G, 111B, M1; ¶0063);
a second transistor (Kim: FIGs. 4-5: M2, 111R, 111G, 111B; ¶0061) configured to transfer a data voltage (Kim: FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) to a source (Kim: FIGs. 4-5: M1’s terminal directly connected to M2, 111R, 111G, 111B; ¶0063) of the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in response to a gate writing signal (Kim: FIGs. 4-5: Sn, 111R, 111G, 111B; ¶0062) of a gate writing signal line (Kim: FIGs. 4-5: line directly connected to Sn, 111R, 111G, 111B; ¶0062);
a third transistor (Kim: FIGs. 4-5: M3, 111R, 111G, 111B; ¶0061) configured to diode-connect the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in response to a gate compensation signal (Kim: FIGs. 4-5: scan signal Sn, 111R, 111G, 111B; ¶0064) of a gate compensation signal line (Kim: FIGs. 4-5: horizontal line directly connected to M3 to provide scan signal Sn, 111R, 111G, 111B; ¶0064); and
a light emitting element (Kim: FIGs. 4-5: OLED, 111R, 111G, 111B; ¶0059) including an anode (Kim: FIGs. 4-5: OLED’s top electrode; ¶0060), and a cathode (Kim: FIGs. 4-5: OLED’s bottom electrode; ¶0060) coupled to a second power supply voltage line (Kim: FIGs. 4-5: Vdd; ¶0059), and
wherein a ratio of a channel width (Kim II: FIG. 4B: horizontal width of CHN3; ¶0082) to a channel length (Kim II: FIG. 4B: vertical length of CHN3; ¶0082) of the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in the third pixel (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is greater than a ratio of a channel width (Jeong: FIG. 4A: horizontal width of CHN1; ¶0082) to a channel length (Jeong: FIG. 4A: vertical length of CHN1; ¶0082) of the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082) in the first pixel (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), and wherein a size of the first capacitor (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP; p 13, ¶2) included in the third pixel (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is determined such that a data voltage range (Jeong: FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the third pixel (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 1-2, 4B: PX3; ¶¶0040, 0048, 0082; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is adjusted close to a data voltage range for the first pixel (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Kim II: FIGs. 2-3: PX1; ¶0083; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Kim II: FIGs. 2-3: PX2; ¶0083; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
8. Claims 1 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2007/0040770 A1 to Kim in view of U.S. Patent Pub. No. 2016/0225318 A1 to Choi in view of Korea Patent Pub. No. 20070035860 A to Jeong et al. (“Jeong”).
As to claim 1, Kim discloses a display panel(100)(FIG. 2; ¶0041) of a display device (FIG. 2; ¶¶0013, 0041), the display panel(100)(FIG. 2; ¶0041) comprising:
a first pixel(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit first color light(red)(FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081, 0088);
a second pixel(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit second color light(green)(FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081, 0088); and
a third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) configured to emit third color light(blue)(FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081, 0088),
wherein each of the first(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081), second(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) and third pixels(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) includes:
a first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) including a first electrode(Cst’s top electrode)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to a first power supply voltage line(Vss)(FIGs. 4-5: 111R, 111G, 111B; ¶0060) and a second electrode(Cst’s bottom electrode)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to a gate node(node N connecting M1’s gate terminal with Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0063);
a first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) including a gate electrode(M1’s gate terminal)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) coupled to the gate node(N)(FIGs. 4-5: 111R, 111G, 111B, M1; ¶0063);
a second transistor(M2)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) configured to transfer a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) to a source(M1’s terminal directly connected to M2)(FIGs. 4-5: 111R, 111G, 111B; ¶0063) of the first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0063) in response to a gate writing signal(Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0062) of a gate writing signal line (line directly connected to Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0062);
a third transistor(M3)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) configured to diode-connect the first transistor(M1)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) in response to a gate compensation signal(scan signal Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0064) of a gate compensation signal line(horizontal line directly connected to M3 to provide scan signal Sn)(FIGs. 4-5: 111R, 111G, 111B; ¶0064); and
a light emitting element(OLED)(FIGs. 4-5: 111R, 111G, 111B; ¶0059) including an anode(OLED’s top electrode)(FIGs. 4-5; ¶0060), and a cathode(OLED’s bottom electrode)(FIGs. 4-5; ¶0060) coupled to a second power supply voltage line (Vdd)(FIGs. 4-5; ¶0059), and wherein a size of the first capacitor(Cst)(FIGs. 4-5: 111R, 111G, 111B; ¶0061) included in the third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) is determined such that a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the third pixel(111B)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081); a data voltage (FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) for the first pixel(111R)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081) or the second pixel(111G)(FIGs. 2, 4-5; ¶¶0043, 0058, 0080-0081).
Kim does not expressly disclose a first capacitor including a first electrode coupled to a first power supply voltage line with no switching element disposed between the first power supply voltage line and the first electrode; and wherein a ratio of a channel width to a channel length of the first transistor in the third pixel is greater than a ratio of a channel width to a channel length of the first transistor in the first pixel or the second pixel, and wherein a size of the first capacitor included in the third pixel is determined such that a data voltage range for the third pixel is adjusted close to a data voltage range for the first pixel or the second pixel.
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Choi discloses and wherein a ratio of a channel width to a channel length (FIG. 10 or FIG. 14; ¶¶0137-0139, 0150-0156 – channel widths {vertical distance of 131aR, 131aG, 131aB} are shown above to be equal {as shown in FIG. 10} or may be set, according to para 0138, as shown in FIG. 8 as: 131aB/blue>131aR/red>131aG/green while channel lengths are shown by the arrowed lines in FIG. 10 as: 131aG/green>131aR/red>131aB/blue}. Alternatively, as shown in FIG. 14, channel widths are 131ab/blue=131aR/red>131aG/green with channel lengths being the same for the blue, red, green pixels) of the first transistor(T1B)(FIG. 10 or FIG. 14; ¶¶0139, 0155) in the third pixel(blue pixel B)(FIG. 10 or FIG. 14; ¶¶0139, 0155) is greater than a ratio of a channel width to a channel length (FIG. 10 or FIG. 14; ¶¶0137-0139, 0150-0156) of the first transistor(T1R, T1G in FIG. 10; T1G in FIG. 14)(FIG. 10 or FIG. 14; ¶¶0139, 0155) in the first pixel(red pixel R)(FIG. 10: T1R; ¶0139) or the second pixel(green pixel G)(FIG. 10 or FIG. 14: T1G; ¶¶0139, 0155).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim with Choi to provide a display panel that is able to display images with minimized color variation between the pixels (¶¶0139, 0156).
Jeong discloses and wherein a size of the first capacitor(Cp)(FIG. 9; p 13, ¶2) included in the third pixel(blue pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is determined such that a data voltage range for the third pixel(blue pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) is adjusted close to a data voltage range for the first pixel(red pixel)(FIG. 9; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) or the second pixel(green pixel)(FIG. 9; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Kim and Choi with Jeong (i.e., to modify the teachings of Kim and Choi by adding a parasitic capacitor Cp to each of the first, second and third pixels) to provide a display panel that may be driven more efficiently with an improved image quality (p 14, ¶2). Below is Kim’s FIG. 5 edited to show the teachings of Jeong.
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Kim, Choi and Jeong teach a display device (Kim: FIG. 2; ¶¶0013, 0041) comprising:
a display panel (Kim: FIG. 2: 100; ¶0041) including a first pixel configured to emit first color light (Kim: FIGs. 2, 4-5: 111R, red; ¶¶0043, 0058, 0080-0081, 0088; Choi: FIG. 10: red pixel R, T1R; ¶0139; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), a second pixel configured to emit second color light (Kim: FIGs. 2, 4-5: 111G, green; ¶¶0043, 0058, 0080-0081, 0088; Choi: FIG. 10 or FIG. 14: green pixel G, T1G; ¶¶0139, 0155; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), and a third pixel configured to emit third color light (Kim: FIGs. 2, 4-5: 111B, blue; ¶¶0043, 0058, 0080-0081, 0088; Choi: FIG. 10 or FIG. 14: blue pixel B; ¶¶0139, 0155; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2);
a data driver (Kim: FIG. 2: 130, 150; ¶¶0048, 0050) configured to provide data voltages (Kim: FIG. 1: 30; ¶¶0043, 0045, 0086) to the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10: red pixel R, T1R; ¶0139; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: green pixel G, T1G; ¶¶0139, 0155; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: blue pixel B; ¶¶0139, 0155; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2);
a scan driver (Kim: FIG. 2: 120, S1 to Sn; ¶0047) configured to provide a gate writing signal (Kim: FIGs. 4-5: Sn, 111R, 111G, 111B; ¶0059), a gate compensation signal (Kim: FIGs. 4-5: scan signal Sn, 111R, 111G, 111B; ¶0064) and a gate initialization signal (Kim: FIGs. 4-5: scan signal Sn-1; ¶0065) to the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10: red pixel R, T1R; ¶0139; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: green pixel G, T1G; ¶¶0139, 0155; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: blue pixel B; ¶¶0139, 0155; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2);
an emission driver (Kim: FIG. 2: 120, E1 to En; ¶0047) configured to provide an emission signal (Kim: FIG. 2: 120, E1 to En; ¶0047) to the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10: red pixel R, T1R; ¶0139; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: green pixel G, T1G; ¶¶0139, 0155; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: blue pixel B; ¶¶0139, 0155; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2); and
a controller (Kim: FIG. 2: 140 or 140 &160; ¶¶0048-0051) configured to control the data driver(Kim: FIG. 2: 130, 150; ¶¶0048, 0050), the scan driver(Kim: FIG. 2: 120, S1 to Sn; ¶0047) and the emission driver (Kim: FIG. 2: 120, E1 to En; ¶0047),
wherein each of the first (Kim: FIGs. 2, 4-5: 111R; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10: red pixel R, T1R; ¶0139; Jeong: FIG. 9: red pixel; p 5, ¶8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2), second (Kim: FIGs. 2, 4-5: 111G; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: green pixel G, T1G; ¶¶0139, 0155; Jeong: FIG. 9: green pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) and third pixels (Kim: FIGs. 2, 4-5: 111B; ¶¶0043, 0058, 0080-0081; Choi: FIG. 10 or FIG. 14: blue pixel B; ¶¶0139, 0155; Jeong: FIG. 9: blue pixel; p 5, ¶¶7-8; p 10, ¶6; p 13, ¶¶6-7; p 14, ¶2) includes:
a first capacitor (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP; p 13, ¶2) including a first electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s bottom electrode; p 13, ¶2) coupled to a first power supply voltage line (Kim: FIGs. 4-5: Vss, 111R, 111G, 111B; ¶0060) with no switching element disposed between the first power supply voltage line (Kim: FIGs. 4-5: Vss, 111R, 111G, 111B; ¶0060) and the first electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s bottom electrode; p 13, ¶2), and a second electrode (Kim: FIGs. 4-5: 111R, 111G, 111B; ¶0061; Jeong: FIG. 9: CP’s top electrode; p 13, ¶2) coupled to a gate node (Kim: FIGs. 4-5: node N connecting M1’s gate terminal with Cst, 111R, 111G, 111B; ¶0063);
a first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Choi: FIG. 10 or FIG. 14: T1B; ¶¶0139, 0155) including a gate electrode (Kim: FIGs. 4-5: M1’s gate terminal, 111R, 111G, 111B; ¶0061) coupled to the gate node (Kim: FIGs. 4-5: N, 111R, 111G, 111B, M1; ¶0063);
a second transistor (Kim: FIGs. 4-5: M2, 111R, 111G, 111B; ¶0061) configured to transfer a data voltage (Kim: FIGs. 4-5: 111R, 111G, 111B, Dmk; ¶0062) to a source (Kim: FIGs. 4-5: M1’s terminal directly connected to M2, 111R, 111G, 111B; ¶0063) of the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Choi: FIG. 10 or FIG. 14: T1B; ¶¶0139, 0155) in response to a gate writing signal (Kim: FIGs. 4-5: Sn, 111R, 111G, 111B; ¶0062) of a gate writing signal line (Kim: FIGs. 4-5: line directly connected to Sn, 111R, 111G, 111B; ¶0062);
a third transistor (Kim: FIGs. 4-5: M3, 111R, 111G, 111B; ¶0061) configured to diode-connect the first transistor (Kim: FIGs. 4-5: M1, 111R, 111G, 111B; ¶0061; Choi: FIG. 10 or FIG. 14: T1B; ¶¶0139, 0155)