DETAILED ACTION
This action is responsive to the communication filed on 5 July 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election of the invention I embodiment in the reply filed on 5 July 2026 is acknowledged.
Because Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant withdrew claims 11-20 in the Response to Election/Restriction filed 5 July 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, and 7-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2021/0343881 (filed July 8, 2021) (hereinafter “Cheng”).
Regarding independent claim 1, Cheng discloses: A trench capacitor, comprising: a semiconductor substrate (FIG. 3, semiconductor substrate 102, [0015]) comprising upwardly protruding structures (FIG. 3, pillar structures 101, [0015]) and first trenches between the upwardly protruding structures (FIG. 3, trenches 102t between the pillar structures 101, [0015]),
wherein each of the upwardly protruding structures has an enlarged head portion (FIG. 3, depicting wherein the pillar structures 101 have enlarged upper portions) and a body portion under the enlarged head portion (FIG. 3, depicting wherein the pillar structures 101 have lower portions under the enlarged upper portions),
wherein the enlarged head portion has a dimension that is greater than a dimension of the body portion (FIG. 3, depicting wherein the enlarged upper portion has a dimension, e.g., width w1, that is greater than a dimension, e.g., width w2 of the lower portion, [0018]);
a dielectric template layer (FIG. 3, insulator layer 108, [0023]) covering the upwardly protruding structures and bottom surfaces of the first trenches (FIG. 3, depicting wherein the insulator layer 108 covers the pillar structures 101 and the trenches 102t),
wherein an outer surface of the dielectric template layer defines second trenches between the upwardly protruding structures (FIG. 3, depicting wherein an outer surface of the insulator layer 108 defines second trenches between the pillar structures 101),
wherein each of the second trenches has a widened lower portion (FIG. 3, depicting the widened lower portion of the trenches defined by the insulator layer 108), a shrunk upper portion (FIG. 3, depicting the shrunk upper portion of the trenches defined by the insulator layer 108), and a middle portion between the widened lower portion and the shrunk upper portion (FIG. 3, depicting the middle portion of the trenches defined by the insulator layer 108 between the widened lower portion and shrunk upper portion);
a capacitor film stack conformally covering the dielectric template layer (FIG. 3, depicting a stack of capacitor layers including, e.g., capacitor electrode layer 110a, capacitor dielectric layer 112a, and capacitor electrode layer 110b, [0023]); and
a sealing layer conformally covering the capacitor film stack (FIG. 3, dielectric layer 114 conformally covering the capacitor layers, [0016]),
wherein the sealing layer seals each of the second trenches at the shrunk upper portion (FIG. 3, depicting wherein the dielectric layer 114 seals the trenches defined by the insulator layer 108), thereby forming stress-releasing voids between the upwardly protruding structures (FIG. 3, depicting cavities 103 between the pillar structures 101, [0019]).
Regarding claim 3, Cheng further discloses wherein the semiconductor substrate is a silicon substrate, and wherein the upwardly protruding structures comprise silicon (FIG. 3, [0022]: “In some embodiments, the semiconductor substrate 102 may, for example, be or comprise a bulk substrate (e.g., bulk silicon), a silicon-on-insulator (SOI) substrate, or another suitable substrate and/or may comprise a first doping type (e.g., p-type). A doped region 104 is disposed within the semiconductor substrate 102 and may comprise the first doping type with a higher doping concentration than the semiconductor substrate 102.”).
Regarding claim 4, Cheng further discloses wherein a bottom surface of each of the first trenches has a concave profile (FIG. 3, depicting wherein a bottom surface of the trenches 102t has a concave profile).
Regarding claim 5, Cheng further discloses wherein the dielectric template layer comprises silicon oxide (FIG. 3, [0023]: “In some embodiments, the insulator layer 108 may, for example, be or comprise an oxide, such as silicon dioxide, or another suitable dielectric material.”).
Regarding claim 7, Cheng further discloses wherein the capacitor film stack comprises a metal-oxide-metal (MIM) film stack (FIG. 3, [0023]: “In some embodiments, the capacitor electrode layers 110 a-d may, for example, respectively be or comprise titanium nitride, tantalum nitride, or the like. In further embodiments, the capacitor dielectric layers 112 a-d may, for example, respectively be or comprise a high-k dielectric material, or some other suitable dielectric material(s). The high-k dielectric material may, for example, be or comprise hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, titanium oxide, or some other suitable high-k dielectric material(s), or any combination of the foregoing.”).
Regarding claim 8, Cheng further discloses wherein the MIM film stack comprises a first electrode layer, a capacitor layer on the first electrode layer, and a second electrode layer on the capacitor layer (FIG. 3, depicting a stack of capacitor layers including, e.g., capacitor electrode layer 110a, capacitor dielectric layer 112a, and capacitor electrode layer 110b).
Regarding claim 9, Cheng further discloses wherein the first electrode layer comprises titanium nitride, the capacitor layer comprises zirconium oxide, aluminum oxide, or a combination thereof, and the second electrode layer comprises titanium nitride (FIG. 3, [0023]: “In some embodiments, the capacitor electrode layers 110 a-d may, for example, respectively be or comprise titanium nitride, tantalum nitride, or the like. In further embodiments, the capacitor dielectric layers 112 a-d may, for example, respectively be or comprise a high-k dielectric material, or some other suitable dielectric material(s). The high-k dielectric material may, for example, be or comprise hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, titanium oxide, or some other suitable high-k dielectric material(s), or any combination of the foregoing.”).
Regarding claim 10, Cheng further discloses wherein the sealing layer comprises silicon oxide (FIG. 3, [0024]: “In some embodiments, the capping dielectric layer 114 may, for example, be or comprise an oxide, such as silicon dioxide, silicon oxynitride, silicon oxycarbide, or another suitable dielectric material.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of U.S. Patent Publication No. 2024/0405062 (filed July 21, 2023) (hereinafter “Kim”).
Regarding claim 2, Cheng does not specifically disclose wherein the enlarged head portion has a hexagonal outline.
In the same field of endeavor, Kim discloses a trench capacitor (FIGS. 5A/5B, depicting a semiconductor device including a trench capacitor, [0006], [0069]-[0070]) including upwardly protruding structures having an enlarged head portion and a body portion under the enlarged head portion (FIGS. 5A/5B, depicting mesh structures M1 and M2 having an enlarged upper portion and a lower portion under the enlarged upper portion, [0068]), wherein the enlarged head portion has a hexagonal outline (FIGS. 5A/5B, depicting wherein the mesh structures M1/M2 have an outline having six angles and six sides, thereby having a hexagonal outline). Regarding the hexagonal, tapered shape of the mesh structures M1 and M2, in [0069], Kim states: “In the case of a trench capacitor, stress due to tensile and compressive stress is applied to the semiconductor substrate S due to a difference between a thermal expansion coefficient of the semiconductor substrate S and thermal expansion coefficients of the dielectric layer and the electrode layer, which are disposed in the trench, so that a cracking problem occurs in the semiconductor substrate S. In order to solve the above problem, in the present embodiment, by forming a void V corresponding to a free space inside the trench, a space is formed to dissipate tensile and compressive stress caused by the difference between the thermal expansion coefficient of the semiconductor substrate S and the thermal expansion coefficients of the dielectric layer and the electrode layer, which are disposed inside the trench (that is, the void V serves as a component for stress relief).”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed trench capacitor of Cheng by substituting the hexagonally shape disclosed in the mesh structures M1/M2 of Kim in order to relieve stress on the layers disposed inside the trench. See Kim [0069]. Moreover, the shape of the englarged head/upper portion of the trench capacitor appears to be a mere matter of design choice of the ordinary skilled artisan, and Applicant does not show that the particular claimed shape of the englarged head/upper portion is significant to the functionality of the device. See MPEP § 2144.04 (I), (IV)(B) (citing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)) (“The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.”); see also MPEP § (IV)(A) (citing Gardner v. TEC Syst., Inc., 725 F.2d 1338 (1984)) (“[T]he Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.”). Rather, the particular hexagonal shape Applicant claims appears to simply be one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of forming a void and in which various capacitor and dielectric layers may be formed in to form a trench capacitor. See In re Dailey, 357 F.2d at 669 (“Appellants have presented no argument which convinces us that the particular configuration of their container is significant or is anything more than one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of providing mating surfaces in the collapsed container of Matzen”).
with the redistribution layer 22 and solder mask 18 of Hsieh in order to route the wiring layers of the image sensor assembly 100a to connectors present on the circuit board. (See Hsieh [0030]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of U.S. Patent Publication No. 2023/0066352 (filed Aug. 27, 2021) (hereinafter “Liu”).
Regarding claim 6, Cheng does not specifically disclose wherein the dielectric template layer has a thickness of 100-200 angstroms.
In the same field of endeavor, Liu discloses a trench capacitor including a dielectric template layer (FIG. 2, dielectric liner 6, [0032]). Regarding the thickness of the dielectric liner, in [0032], Kuo states: “The dielectric liner 6 may include a dielectric material that provides electrical isolation between the first deep trench capacitors to be subsequently formed and the first substrate 8.” Kuo further states in [0032]: “The thickness of the dielectric liner 6 may be in a range from 4 nm [40 angstroms] to 100 nm [1000 angstroms], although lesser and greater thicknesses may also be used.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the trench capacitor of Cheng by substituting the dielectric layer thickness of Liu in order to sufficiently electrically isolate the capacitors and substrate. See Liu [0032]; see also MPEP § 2144.05 (“In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art' a prima facie case of obviousness exists.”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication Nos.: 2023/0069538 (filed Aug. 27, 2021) (disclosing a void containing trench capacitor structure); 2023/0009279 (filed Jan. 31, 2022) (disclosing a concave, void containing trench capacitor structure).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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