Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
DETAILED ACTION
In response to the Communications dated May 27, 2024, claims 3-22 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 3 and 13, the phrase “each of the second subset of the second terminals is coupled to at least one memory device of the one or more second memory devices and not coupled to any of the one or more second memory devices” does not make sense. It recites that the terminals are connected to a second memory device, but is not connected to any second memory devices.
The dependent claims are rejected because the depend on the indefiniteness of the claims from which they depend.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 3 and 13 are rejected, as understood, on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11994982 [‘982]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘982
3. (New) A memory module operable in a computer system to communicate with a memory controller of the computer system via a memory bus having signal lines including system control/address (C/A) signal lines and system data signal lines, the memory module comprising: a module board having electrical contacts, the electrical contacts including C/A contacts via which the memory module receives input C/A signals and data contacts via which the memory module receives and/or outputs data signals, the C/A contacts corresponding, respectively, to the system C/A signal lines, and the data contacts corresponding, respectively, to the system data signal lines; a module control device mounted on the module board and coupled to the C/A contacts; memory devices mounted on the module board and coupled to the module control device, the memory devices including a first plurality of memory devices and a second plurality of memory devices; and data buffers mounted on the module board at corresponding positions that are spaced apart from each other, a first data buffer of the data buffers having first control inputs coupled to the module control device, first terminals coupled to a first subset of the data contacts, and second terminals coupled to a first subset of the memory devices, the first subset of the memory devices including one or more first memory devices and one or more second memory devices, the one or more first memory devices including at least one first memory device from the first plurality of memory devices, the one or more second memory devices including at least one second memory device from the second plurality of memory devices, the first data buffer including a first n-bit-wide write path coupled to a first subset of the second terminals and a second n-bit-wide write path coupled to a second subset of the second terminals, » being a positive integer; wherein: each of the first subset of the second terminals is coupled to at least one memory device of the one or more first memory devices and not coupled to any of the one or more second memory devices;
each of the second subset of the second terminals is coupled to at least one memory device of the one or more second memory devices and not coupled to any of the one or more second memory devices; the module control device is configurable to receive first input C/A signals for a first write operation to write first data to the memory module, the first input C/A signals targeting the first plurality of memory devices among the memory devices to receive and store the first data; the module control device is further configurable to output first module C/A signal and first module control signals in response to the first input C/A signals; the first data buffer is configurable, in response to the first module control signals, to receive a first n-bit-wide section of the first data via the first terminals and to select the first n- bit-wide write path to transmit the first n-bit-wide section of the first data, whereby each data bit associated with the first write operation and received by the first data buffer is transmitted to a corresponding terminal of the first subset of the second terminals and not to any of the second subset of the second terminals; and the at least one first memory device is configurable to receive the first n-bit-wide section of the first data from the first data buffer in response to at least some of the first module C/A signals.
1. A memory module operable in a computer system, the computer system including address and control signal lines, data signal lines, one or more module slots for mounting one or more memory modules, and a memory controller configurable to communicate with each of the one or more memory modules via the address and control signal lines and the data signal lines, the memory module comprising: a module board having an edge connector including a plurality of electrical contacts to be releasably coupled to corresponding contacts of a module slot of the one or more module slots; memory devices arranged in multiple N-bit-wide ranks on the module board; a module controller on the module board configurable to receive via the address and control signal lines address and control signals for a memory read or write operation, and to output, first module control signals associated with the memory read or write operation and second module control signals associated with the memory read or write operation, wherein, in response to the first module control signals associated with the memory read or write operation, one of the multiple N-bit-wide ranks is selected to perform the memory read or write operation by outputting or receiving N-bit-wide data associated with the memory read or write operation; and data buffers distributed along the edge connector of the module board and coupled to the memory devices via module data lines, each respective data buffer being configurable to buffer and transmit a respective n-bit-wide section of the N-bit-wide data between a respective n-bit-wide section of the module data lines and a respective n-bit-wide section of the data signal lines, the respective n-bit-wide section of the data signal lines including a first data signal line, the respective n-bit-wide section of the module data lines including a first module data line corresponding to the first data signal line, the respective data buffer including respective data paths and respective logic configurable to control the respective data paths in response to the second module control signals from the module controller, the respective data paths including a first write data path and a first read data path between the first module data line and the first data signal line, the first write data path including a write input buffer coupled to the first data signal line and a write output driver coupled to the first module data line, the first read data path including a read input buffer coupled to the module data line and a read output driver coupled to the data signal line, wherein, in response to the memory read or write operation being a memory write operation, the respective logic is configured to cause the first write data path to transition from a first configuration to a second configuration and subsequently from the second configuration to the first configuration, wherein the first write data path is disabled in the first configuration and is enabled in the second configuration to receive a first write data bit of a respective n-bit-wide section of N-bit-wide write data from the first data signal line, to pass the first write data bit through the first write data path from the write input buffer to the write output driver, and to drive the first write data bit to the first module data line, wherein, in response to the memory read or write operation being a memory read operation, the respective logic is configured to cause the first read data path to transition from a third configuration to a fourth configuration and subsequently from the fourth configuration to the third configuration, wherein the first read data path is disabled in the third configuration and is enabled in the fourth configuration to receive a first read data bit of a respective n-bit-wide section of N-bit-wide read data from the first module data line, to pass the first read data bit through the first read data path from the read input buffer to the read output driver, and to drive the first read data bit to the first data signal line, wherein N and n are positive integers and n is less than N; wherein the first read data path is kept at the third configuration during the memory write operation, and the first write data path is kept at the first configuration during the memory read operation; and wherein: the first write data path is distinct from the first read data path such that, during the memory write operation, the first write data bit is passed from the write input buffer to the write output driver without passing through any portion of the first read data path between the read input buffer and the read output driver, and that, during the memory read operation, the first read data bit is passed from the read input buffer to the read output driver without passing through any portion of the first write data path between the write input buffer and the write output driver; and the write output driver is tristated when the first write data path is in the first configuration, and the read output driver is tristated when the first read data path is in the third configuration.
13. (New) A memory module operable in a computer system to communicate with a memory controller of the computer system via a memory bus having signal lines including system control/address (C/A) signal lines and system data signal lines, the memory module comprising: a module board having electrical contacts, the electrical contacts including C/A contacts via which the memory module receives input C/A signals and data contacts via which the memory module receives and/or outputs data signals, the C/A contacts corresponding, respectively, to the system C/A signal lines, and the data contacts corresponding, respectively, to the system data signal lines;
a module control device mounted on the module board and coupled to the C/A contacts; memory devices mounted on the module board and coupled to the module control device, the memory devices including a first plurality of memory devices and a second plurality of memory devices; and
data buffers mounted on the module board at corresponding positions that are spaced apart from each other, a first data buffer of the data buffers having first control inputs coupled to the module control device, first terminals coupled to a first subset of the data contacts, and second terminals coupled to a first subset of the memory devices, the first subset of the memory devices including one or more first memory devices and one or more second memory devices, the one or more first memory devices including at least one first memory device from the first plurality of memory devices, the one or more second memory devices including at least one second memory device from the second plurality of memory devices, the first data buffer including a first n-bit-wide write path coupled to a first subset of the second terminals and a second n-bit-wide write path coupled to a second subset of the second terminals, » being a positive integer; wherein: each of the first subset of the second terminals is coupled to at least one memory device in the one or more first memory devices and not coupled to any of the one or more second memory devices; each of the second subset of the second terminals is coupled to at least one memory device in the one or more second memory devices and not coupled to any of the one or more second memory devices; the module control device is configurable to receive first input C/A signals for a first write operation to write first data to the memory module and subsequently second input C/A signals for a second write operation to write secibd data to the memory module, the first input C/A signals targeting the first plurality of memory devices among the memory devices to receive and store the first data, the second input C/A signals targeting the second plurality of memory devices among the memory devices to receive and store the second data;
the module control device is further configurable to output first module C/A signal and first module control signals in response to the first input C/A signals, and to output second module C/A signals and second module control signals in response to the second input C/A signals; the first data buffer is configurable, in response to the first module control signals, to receive a first n-bit-wide section of the first data via the first terminals and to select the first n- bit-wide write path to transmit the first 7-bit-wide section of the first data, whereby each data bit associated with the first write operation and received by the first data buffer is transmitted to a corresponding terminal of the first subset of the second terminals and not to any of the second subset of the second terminals; the first data buffer is further configurable, in response to the second module control signals, to receive a first n-bit-wide section of the second data via the first terminals and to select the second n-bit-wide write path to transmit the first n-bit-wide section of the second data, whereby each data bit associated with the second write operation and received by the first data buffer is transmitted to a corresponding terminal of the second subset of the second terminals and not to any of the first subset of the second terminals;
the at least one first memory device is configurable to receive the first n-bit-wide section of the first data from the first data buffer in response to at least some of the first module C/A signals; and the at least one second memory device is configurable to receive the first n-bit-wide section of the second data from the first data buffer in response to at least some of the second module C/A signals.
See claim 1 and below remarks.
As can be seen from the above table, similar to the patent, the application recites, in claims 3 and 13, a memory module comprising: a module board, a module control device, memory devices and data buffers. Unlike the patent, the application recites that the module control device, memory devices and data buffers are mounted on the module board; whereas, the patent recites, in claim 1, that the respective components are arranged and disposed on the module board. It is reasonable to interpret that the recitations are similar because all of the components are on the board. Additionally, the application recites configurable terminals and contacts as applied to the equivalent of the patent’s configurable data paths. Further, the patent recites, in further details, of the structural and functionality of the respective components. For example, the patent recites “…each respective data buffer being configurable to buffer and transmit a respective n-bit-wide section of the N-bit-wide data between a respective n-bit-wide section of the module data lines and a respective n-bit-wide section of the data signal lines…” It is reasonable to interpret that this recitation covers the same recitation of the application, in that, the patent indicates that it may be configure to connect subsets of a plurality of memory devices. Since the claim of the patent is more limited, it would encompass all limitations of the claim of the present application. Therefore, the patent protections have been granted to the earlier filed patent application.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 2, 2026