DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 and 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida (U.S. Publication No. 2020/0365715 A1).
With respect to claim 1, Yoshida discloses a semiconductor device comprising a diode portion, comprising: a plurality of trench portions [30] provided at a front surface of a semiconductor substrate [10]; a drift region [18] of a first conductivity type [N] provided on the semiconductor substrate; an anode region [14] of a second conductivity type [P] provided above the drift region in the diode portion; a first plug region [17] of the second conductivity type which is provided above the drift region in the diode portion and has a doping concentration higher than a doping concentration of the anode region (see ¶[0076]; P- vs P+); a front surface side electrode [52] provided above the semiconductor substrate; and an interlayer dielectric film [38] provided above a mesa portion [61] provided between the plurality of trench portions; wherein the anode region is connected to the front surface side electrode on side surfaces of the plurality of trench portions (See Figure 3; ¶[0076]).
With respect to claim 2, Yoshida discloses comprising above the mesa portion, a first contact portion [54] being extended in a trench extending direction of the plurality of trench portions and connected to the anode region and the first plug region (see figure 3).
With respect to claim 3, Yoshida discloses comprising a second contact portion that is extended, on the front surface of the semiconductor substrate, from one side wall of a trench portion among the plurality of trench portions to another side wall of a trench portion in a trench array direction of the plurality of trench portions, and connected to the mesa portion (see Figure 3).
With respect to claim 4, Yoshida discloses wherein the second contact portion is extended, in the trench array direction of the plurality of trench portions, beyond at least one trench portion of the plurality of trench portions, and connected to the at least one trench portion (see Figure 3).
With respect to claim 5, Yoshida discloses wherein a width of the first contact portion in the trench array direction is greater than a width of the second contact portion in the trench extending direction (see Figure 2).
With respect to claim 6, Yoshida discloses wherein the second contact portion is provided above the anode region and the plurality of trench portions alternately provided in the trench array direction (see Figures 2-3).
With respect to claim 7, Yoshida discloses wherein a plurality of the second contact portions are provided above the anode region and the plurality of trench portions alternately provided in the trench array direction (see Figure 2-3).
With respect to claim 8, Yoshida discloses wherein the interlayer dielectric film [38] has a first interlayer dielectric portion provided between the first plug region [17] and the plurality of trench portions in the trench array direction, in a top view (See Figures 2-3)
With respect to claim 9, Yoshida discloses wherein the interlayer dielectric film has a second interlayer dielectric (directly above [42]) portion provided between the anode region and the plurality of trench portions in the trench array direction, in a top view (see Figure 2-3)
With respect to claim 10, Yoshida discloses wherein a width of the first interlayer dielectric portion in the trench extending direction is greater than a width of the second interlayer dielectric portion in the trench extending direction (See Figures 2-3).
With respect to claim 11, Yoshida discloses wherein the first interlayer dielectric portion is sandwiched, in the trench array direction, between a plurality of the first contact portions being extended in the trench extending direction; and the first interlayer dielectric portion is sandwiched, in the trench extending direction, between a plurality of the second contact portions being extended in the trench array direction (see Figures 2-3).
With respect to claim 12, Yoshida discloses wherein the second interlayer dielectric portion is sandwiched, in the trench array direction, between a plurality of the first contact portions being extended in the trench extending direction; and the second interlayer dielectric portion is sandwiched, in the trench extending direction, between a plurality of the second contact portions being extended in the trench array direction (see Figures 2-3).
With respect to claim 13, Yoshida discloses wherein the front surface side electrode has a barrier metal layer provided inside the first contact portion and the second contact portion (See ¶[0053]).
With respect to claim 19, Yoshida discloses wherein the first plug region is provided to be spaced apart from a trench sidewall of the plurality of trench portions in a trench array direction of the plurality of trench portions; the anode region is provided to be extended from one trench sidewall of the plurality of trench portions to another trench sidewall in the trench array direction; and the first plug region and the anode region are alternately provided in a trench extending direction of the plurality of trench portions in the mesa portion (See Figures 2-3).
With respect to claim 20, Yoshida discloses wherein in the mesa portion, an area of the anode region on the front surface of the semiconductor substrate is greater than an area of the first plug region on the front surface of the semiconductor substrate (see Figure 3).
With respect to claim 21, Yoshida discloses wherein The front surface side electrode has a plug layer composed of tungsten (see ¶[0053]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14, 16-18 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Muramatsu et al (U.S. Publication No. 2023/0299077 A1; hereinafter Muramatsu).
With respect to claim 14, Yoshida discloses comprising a transistor portion [70] having a base region [14] of the second conductivity type provided above the drift region, but fails to disclose wherein a doping concentration of the anode region is lower than a doping concentration of the base region. In the same field of endeavor, Muramatsu teaches a transistor portion [73] having a base region [14] of the second conductivity type provided above the drift region, wherein a doping concentration of the anode region [84] is lower than a doping concentration of the base region (See Figure 1C; ¶[0075-0076]). Implementation of a lower doping concentration of the anode region than that of the base region increases hole density, thereby allowing for large reverse recovery peak current (See Muramatsu ¶[0078]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 16, the combination of Yoshida and Muramatsu discloses a second plug region [19] of the second conductivity type which is provided above the drift region in the transistor portion and has a doping concentration higher than a doping concentration of the base region (see Muramatsu Figure 1B).
With respect to claim 17, Yoshida fails to disclose wherein the doping concentration of the anode region is 4E16 cm−3 or more or 1E17 cm−3 or less In the same field of endeavor, Muramatsu teaches wherein the doping concentration of the anode region is 4E16 cm−3 or more or 1E17 cm−3 or less (See ¶[0060]). Implementation of a proper concentration of dopants for the anode region, as taught by Muramatsu, increases hole density, thereby allowing for large reverse recovery peak current (See Muramatsu ¶[0078]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 18, Yoshida fails to disclose wherein the doping concentration of the first plug region is 2E19 cm−3 or more or 2E20 cm−3 or less. In the same field of endeavor, Muramatsu teaches wherein the doping concentration of the first plug region is 2E19 cm−3 or more or 2E20 cm−3 or less (see ¶[0089])
Implementation of a proper concentration of the plug region as taught by Muramatsu allows for suppression of latch-up by extracting the minority carrier (see ¶[0089]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 22, Yoshida discloses a cathode region [82] of the first conductivity type provided on a back surface of the semiconductor substrate in the diode portion; but fails to disclose wherein a doping concentration of the cathode region is 5E19 cm−3 or more or 2E20 cm−3 or less. In the same field of endeavor, Muramatsu teaches wherein a doping concentration of the cathode region is 5E19 cm−3 or more or 2E20 cm−3 or less (See ¶[0060] and ¶[0102]).
Implementation of a proper doping concentration of the cathode region as taught by Muramatsu facilitates proper electron current flow within the device (see ¶[0078]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Muramatsu as applied to claim 14 above, and further in view of Kubouchi (U.S. Publication No. 2022/0375933 A1).
With respect to claim 15, the combination of Yoshida and Muramatsu discloses a contact region [15] of the second conductivity type provided above the drift region in the transistor portion but fails to disclose wherein the doping concentration of the first plug region is higher than a doping concentration of the contact region. In the same field of endeavor, Kubouchi teaches wherein the doping concentration of the first plug region [17] is higher than a doping concentration of the contact region [15] (see ¶[0090]). Implementation of a higher doping concentration of the plug region than that of the contact region as taught by Kubouchi improves contact resistance (See ¶[0067). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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