Prosecution Insights
Last updated: August 17, 2026
Application No. 18/675,167

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Non-Final OA §102
Filed
May 28, 2024
Priority
Apr 10, 2024 — TW 113113244
Examiner
SUN, YU-HSI DAVID
Art Unit
Tech Center
Assignee
Hon Hai Precision Industry Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
673 granted / 871 resolved
+17.3% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
892
Total Applications
across all art units

Statute-Specific Performance

§101
3.6%
-36.4% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 871 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, Species I in the reply filed on 7/14/2026 is acknowledged. Claims 5-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/14/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo et al. (US PG Pub 2022/0302291, hereinafter Guo). Regarding claim 1, figure 5I of Guo discloses a semiconductor structure, comprising: a substrate (112); a semiconductor layer (116) on the substrate; a gate structure (126) on the semiconductor layer; a first dielectric layer (121) continuously extending on the gate structure and the semiconductor layer, wherein the first dielectric layer comprises a first portion and a second portion; an etch stop layer (123) on at least the first portion of the first dielectric layer; a second dielectric layer (147) on the etch stop layer; and a field plate (140) comprising a first field plate portion on the second dielectric layer and a second field plate portion on the second portion of the first dielectric layer, wherein a lower surface of the first field plate portion is a first distance away from the semiconductor layer, a lower surface of the second field plate portion is a second distance away from the semiconductor layer, the first distance is larger than the second distance, the field plate has a first projection on the substrate along a vertical direction of the substrate, the gate structure has a second projection on the substrate along the vertical direction of the substrate, and the first projection does not cover the second projection. Regarding claim 2, figure 5I of Guo discloses the field plate (140) extends continuously on the first dielectric layer (121) and the second dielectric layer (147). Regarding claim 3, figure 5I of Guo discloses a third dielectric layer on the first dielectric layer and the second dielectric layer, wherein the field plate is on the third dielectric layer (¶ 55, last sentence). Regarding claim 4, figure 5I of Guo discloses an upper surface of the second portion of the first dielectric layer (121) is lower than an upper surface of the first portion of the first dielectric layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 28, 2024
Application Filed
Jul 29, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707750
IMAGING ELEMENT AND ELECTRONIC APPARATUS
2y 8m to grant Granted Aug 11, 2026
Patent 12708051
SEMICONDUCTOR PACKAGE
2y 4m to grant Granted Aug 11, 2026
Patent 12702037
BONDING APPARATUS, BONDING METHOD, AND COMPUTER READABLE STORAGE MEDIUM
3y 2m to grant Granted Aug 04, 2026
Patent 12696762
POWER SEMICONDUCTOR MODULE COMPRISING AT LEAST ONE POWER SEMICONDUCTOR ELEMENT
3y 7m to grant Granted Jul 28, 2026
Patent 12690489
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
3y 11m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
86%
With Interview (+8.5%)
2y 8m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 871 resolved cases by this examiner. Grant probability derived from career allowance rate.

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