DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 5 and 8-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/04/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/28/2024, 01/21/2025, 02/27/2025, 02/10/2026 and 05/04/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US20220293779, Du herein after) in view of Hwang et al. (US20240274673, Hwang herein after).
Regarding claim 1, Du teaches a semiconductor structure, comprising:
a substrate (¶ [0028]: the substrate 102);
a semiconductor layer (¶ [0028]: composite layer including semiconductor channel layer 106 and semiconductor barrier layer 108) on the substrate (Fig. 1, 106 and 108 are stacked on substrate 102);
a gate structure (¶ [0028]: at least one of 110, 120 and/or 121; gate electrode 120, gate field plate 121; ¶ [0034]: the gate electrode 120 may be electrically connected to the underlying semiconductor capping layer 110) on the semiconductor layer (Fig.1, 120, 121 and/or 110 are on the semiconductor layer 106 );
a first dielectric layer (¶ [0029]: a first interlayer dielectric layer 162) continuously extending on the gate structure and the semiconductor layer (Fig.1, the first dielectric layer 162 is continuously extending on gate 120 and semiconductor channel layer 106),
wherein the first dielectric layer comprises a first portion, a second portion, and a third portion (see annotated Fig.1, respective portions of 162 disposed in region 1, region 2 and region 3), the third portion is on an upper surface of the gate structure (see annotated Fig.1: portion of 162 in region 3 is on gate 110/120/121), and the second portion is closer to the third portion than the first portion (annotated Fig. 1 (162), lateral distance between 2nd and 3rd region is less than distance between 1st and 3rd);
a second dielectric layer (¶ [0029]: a second interlayer dielectric layer 164);
and a field plate (¶ [0029]: a third field plate 135) comprising a first field plate portion on the second dielectric layer (see annotated Fig.1, portion of 135 in region 1 is on dielectric layer 164) and a second field plate portion and a third field plate portion respectively on the second portion and the third portion of the first dielectric layer (see annotated Fig. 1, portion of 135 in region 2 and region 3 are on 164)
wherein a lower surface of the first field plate portion is a first distance (annotated Fig.1, D1) away from the semiconductor layer, a lower surface of the second field plate portion is a second distance (annotated Fig. 2, D2) away from the semiconductor layer, the first distance is larger than the second distance (annotated Fig. 1, D1 is larger than D2),
the field plate has a first projection on the substrate along a vertical direction of the substrate (thickness of 135 in region 3), the gate structure has a second projection on the substrate along the vertical direction of the substrate (thickness of 110/120/121 in region 3), and the first projection completely covers the second projection. (Fig.1, 135 in region 3 completely covers 110/120/121 in region 3).
Du further teaches a photolithographic process including an etch process (¶ [0048]: “ Afterwards, photolithography and etching processes may be performed to etch the first interlayer dielectric layer 162”).
However, Du does not teach an etch stop layer on at least the first portion of the first dielectric layer, and the second dielectric layer disposed on the etch stop layer.
Hwang teaches a semiconductor structure including etch stop layer (¶ [0040]: etch stop layer 118a) on at least a first portion of a first dielectric layer (Fig. 1H, etch stop 118a is on the dielectric layer 116; 116 is similar to 162 of Du), and a second dielectric layer (¶ [0043]: a dielectric layer120a; 120a is similar to 164 of Du) on the etch stop layer (Fig. 1H, dielectric layer 120a is on the etch stop layer 118a).
Since Du and Hwang are in the same field of HEMT, a person having ordinary skill in the art at the time of filing would have recognized the desirability and advantages of modifying Du, as suggested by Hwang, by employing an etch stop layer on the first dielectric layer. This etch stop layer would prevent the erosion of the first dielectric layer from the etching process in the photolithography step of Du. The etch stop layer can also shape the pattern of the second dielectric layer. (Hwang, ¶ [0043]: “a dry etching process may be performed on the dielectric material layer 120 by using the patterned photoresist layer 122 as a mask and using the etch stop material layer 118 as an etch stop layer to remove the portion of the dielectric material layer 120. Therefore, the dielectric material layer 120 may be patterned to form the dielectric layer 120a and to expose the etch stop material layer 118.”)
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Regarding claim 2, Du in view of Hwang teach the semiconductor structure of claim 1, wherein the field plate extends continuously on the first dielectric layer and the second dielectric layer. (Du, Fig. 1, field plate 135 extends continuously in the x-direction on at least portions of dielectric layers 162 and 164)
Regarding claim 3, Du in view of Hwang teach the semiconductor structure of claim 1, wherein a projection of the second dielectric layer on the substrate along the vertical direction of the substrate (Du, annotated Fig.1, thickness of 164) overlaps with a projection of the first portion of the first dielectric layer on the substrate along the vertical direction of the substrate (Du, annotated Fig. 1, 164 overlaps 162 in at least region 1) , and the projection of the second dielectric layer on the substrate along the vertical direction of the substrate does not overlap with a projection of the second portion and the third portion of the first dielectric layer on the substrate along the vertical direction of the substrate. (Du, annotated Fig. 1, portion of 164 in region 1 does not overlap portions of 162 in region 2 and region 3)
Regarding claim 4, Du in view of Hwang teach the semiconductor structure of claim 1, wherein a lower surface of the third field plate portion is a third distance away (Du, annotated Fig. 1, D3) from the semiconductor layer, and the third distance is larger than the second distance (Du, annotated Fig.1, D3 is larger than D2).
Regarding claim 6, Du in view of Hwang teach the semiconductor structure of claim 1, wherein an upper surface of the second portion (Du, annotated Fig. 1, S2) of the first dielectric layer is lower than an upper surface of the first portion (Du, annotated Fig. 1, S1) of the first dielectric layer. (Du, annotated Fig. 1, S2 is at a lower height to substrate than S1)
Regarding claim 7, Du in view of Hwang teach the semiconductor structure of claim 1, wherein the gate structure comprises a doped layer (Du, ¶ [0033]: The semiconductor capping layer 110 may be one or more layers of doped group III-V semiconductor layers, for example, a p-type group III-V semiconductor layer) and a metal layer (Du, ¶ [0034]: The composition of the gate electrode 120 may be, for example, TiN, W, Pt, Ni, Ti, Al, Au, Mo) on the doped layer (Du, Fig.1, 120 is on 110),
and the semiconductor layer comprises a channel layer (Du, ¶ [0028]: a semiconductor channel layer 106) and a barrier layer (Du, ¶ [0028]: a semiconductor barrier layer 108) on the channel layer (Du, Fig. 1, 108 is on 106).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (US 2016/0043184 A1) teaches a 2nd dielectric layer overlapping a first portion of a first dielectric layer but not overlapping second and third portions of the first dielectric layer (Fig. 5B) as recited in claim 3.
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/BRIAN TURNER/Examiner, Art Unit 2818
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