The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s election without traverse of Invention I (claims 1-14 and 21-26) in the reply filed on January 19, 2026 is acknowledged.
Claims 1 and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 8, and 17 of U.S. Patent No. 12,035,104. Although the claims at issue are not identical, they are not patentably distinct from each other because: as noted by the Federal Circuit in Eli Lilly v. Barr, “[a] a patentable distinction does not lie where a later claim is anticipated by an earlier one” (see also In re Berg and In re Goodman which established that a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim). Specifically, the patent claims 1, 6, 8, and 17 recite each and every limitation recited in the application claims. Patent claims 1 and 6 recite each and every limitation of application claim 1, and patent claims 8 and 17 recite each and every limitation of application claim 8.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 8, 9, 11, 21, 22, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. (US 8,723,241) considered with Wang (US 7,910,968).
Regarding claim 1, Udayakumar discloses an integrated circuit (IC) chip (see figure 2G, for example), comprising: a piezoelectric device 240 (includes conductive hard mask 236, second electrode 234, ferroelectric element 232, and first electrode 230; see col. 8, lines 50-53) overlying a substrate 202; a first (left-side) pad 246 overlying the piezoelectric device 240; a first (left-side) via 244 extending from the first pad 246 to the piezoelectric device 240; a second (right-side) pad 246 overlying the piezoelectric device 240; a second (right-side) via 244 extending from the second pad 246 to the piezoelectric device 240; and a barrier layer 238, wherein the barrier layer 238 is configured to block hydrogen ions from diffusing through the barrier layer 238, from over the barrier layer 238 to the piezoelectric device 240.
Regarding claim 8, Udayakumar discloses an integrated circuit (IC) chip (see figure 2G, for example), comprising: a piezoelectric device 240 overlying a substrate 202, wherein the piezoelectric device 240 comprises a bottom electrode 230, a piezoelectric layer 232 overlying the bottom electrode 230, and a top electrode 234 overlying the piezoelectric layer 232; a pad 246 overlying and spaced from the piezoelectric device 240; a via 244 extending from the pad 246 to the bottom electrode 230, or to the top electrode 234, of the piezoelectric device 240; and a barrier layer 238, wherein the barrier layer 238 is configured to block hydrogen ions from diffusing through the barrier layer 238, from over the barrier layer 238 to the piezoelectric device 240.
Regarding claim 21, Udayakumar discloses an integrated circuit (IC) chip (see figure 2G, for example), comprising: a substrate 202 comprising a moveable membrane 268 at an opening, which extends through the substrate 202 (see col. 3, lines 37-40, regarding “the flexible element may take the form of a membrane, with a base disposed around a periphery of the flexible element and the proof mass disposed at a central region of the flexible member”); a piezoelectric device 240 overlying the substrate 202 and extending in a closed path around the moveable membrane 268 when viewed top down as claimed (see fig. 14, for example, wherein any one of piezoelectric elements 1408 can be considered to extend in closed path around moveable membrane when viewed top down as claimed); a pad 246 (e.g., the pad 246 , with connecting via 244, located on right side of IC chip) overlying the piezoelectric device 240 and extending to a location laterally offset from the piezoelectric device 240; a first barrier layer 238 between the pad 246 and the piezoelectric device 240; and a via 244 extending through the first barrier layer 238, from the pad 246 to the piezoelectric device 240.
Udayakumar discloses the invention as claimed, but fails to specifically teach that the integrated circuit (IC) chip further includes an additional (second) barrier layer overlying the pad(s), wherein the additional (second) barrier layer is configured to block hydrogen ions from diffusing through the additional (second) barrier layer, from over the barrier layer to the piezoelectric device 240, and wherein both barrier layers have the same material composition. Wang discloses an integrated circuit (IC) chip (see fig. 5, for example) comprising a ferroelectric device (i.e., a ferroelectric film 38 between a pair of electrodes 36, 40 similar to layered structure of the claimed piezoelectric device) overlying a substrate 10, and a via 34 extending from an electrical pad 58 to the ferroelectric device, wherein the IC chip further includes a plurality of barrier layers 46, 50, 84, 86, 90, of similar material composition overlying the ferroelectric device, wherein one barrier layer (e.g., barrier layer 84, 86, or 90) overlies the electrical pad 58, in the same field of endeavor, for the purpose of obtaining a higher hydrogen barrier property by forming a larger number of barrier layers within the IC chip (see col. 13, lines 14-17).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Udavakumar, in view of Wang, such that the integrated circuit (IC) chip further includes an additional (second) barrier layer overlying the pad(s) 246, wherein the additional (second) barrier layer is configured to block hydrogen ions from diffusing through the additional (second) barrier layer, from over the barrier layer to the piezoelectric device 240, and wherein both barrier layers have the same material composition. A practitioner in the art would have been motivated to do this for the purpose of obtaining a higher hydrogen barrier property by forming an additional barrier layer overlying the pad(s) 246 within the IC chip, thereby more effectively blocking hydrogen ions from diffusing through the additional barrier layer, from over the additional barrier layer to the piezoelectric device.
Regarding claim 2, Udavakumar, as modified by Wang above, discloses an IC chip (see Udavakumar, fig. 2G, for example), wherein the barrier layer 238 can be considered the additional barrier layer as claimed, wherein the additional barrier layer 238 is between the first (left-side) pad 246 and the piezoelectric device 240, wherein the first (left-side) via 244 extends through the additional barrier layer 238, and wherein the additional barrier layer 238 is configured to block hydrogen ions from diffusion through the additional barrier layer 238, from over the additional barrier layer 238 to the piezoelectric device 240.
Regarding claim 5, the substrate 202 comprises a movable membrane 268 at an opening extending through the substrate 202. The piezoelectric device 240 extends in a closed path around the moveable membrane 268 as claimed. See Udavakumar, fig. 14, for example, wherein any one of piezoelectric elements 1408 can be considered to extend in closed path around moveable membrane as claimed.
Regarding claim 9, the entirety of the via 244 (e.g., the via 244, located on left side of IC chip) overlies the piezoelectric device 240.
Regarding claim 11, the pad 246 (e.g., the pad 246, located on right side of IC chip) has a first (left) end directly over and electrically coupled to the piezoelectric device 240 by the via 244. The pad 246 further has a second (right) end that is distal from the first (left) end and laterally offset from the piezoelectric device 240.
Regarding claim 22, a dielectric layer 242 is between and contacting the pad 246 and the first barrier layer 238, which contacts the piezoelectric device 240.
Regarding claim 25, the first barrier layer 238 has a sidewall overlying the piezoelectric device 240. See Udavakumar, fig. 2G, for example. The sidewall of the first barrier layer 238 is closer to a width-wise center of the piezoelectric device 240 than to a periphery of the piezoelectric device 240 as claimed.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. (US 8,723,241) considered with Wang (US 7,910,968), as applied to claim 1 above, in further view of Shih et al. (US 2021/0043721).
Udayakumar, as modified and applied to claim 1 above, discloses the invention as claimed, but fails to specifically teach that the IC chip (see Udavakumar, fig. 2G, for example) further includes a getter layer underlying and directly contacting the piezoelectric device 240, wherein the getter layer has a width greater than a width of the piezoelectric device 240 and is configured to getter hydrogen ions. Shih discloses an integrated circuit (IC) chip (see fig. 2C, for example) comprising a MIM device (e.g., a dielectric layer 106 arranged between top and bottom electrodes 108, 104), and further including a getter layer 110 underlying and directly contacting the MIM device and is configured to getter hydrogen ions, in the same field of endeavor, for the purpose of absorbing hydrogen ions thereby preventing damage to the MEM device (see para. 0001).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to further modify Udayakumar, in view of Shih, such that the bottom barrier layer 228 is replaced with a getter layer, wherein the getter layer underlies and directly contacts the piezoelectric device 240, wherein the getter layer has a width greater than a width of the piezoelectric device 240 and is configured to getter hydrogen ions. A practitioner in the art would have been motivated to do this for the purpose of using a getter layer, rather than the barrier layer 228, to further prevent hydrogen from diffusing into the piezoelectric device 240 and causing damage.
Further regarding claim 4, the getter layer consists essentially of a metal element (see Shih, para. 0019, regarding the metal element being titanium). The barrier layer comprises a metal oxide (see Udayakumar, col. 5, lines 48-49, regarding the metal oxide being aluminum oxide). The metal oxide comprises a metal element (aluminum) different than the metal element (titanium) of the getter layer.
Claims 12 rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. (US 8,723,241) considered with Wang (US 7,910,968), as applied to claim 8 above, in further view of Bakke et al. (US 9,329,360).
Udayakumar, as modified and applied to claim 8 above, discloses the invention as claimed, including using a plurality of piezoelectric elements 1408 that surrounds an opening extending through the substrate 202 (see Udayakumar, fig. 14, for example), but fails to specifically teach that the piezoelectric device 240 has a ring-shaped top geometry that surrounds an opening extending through the substrate 202. Bakke discloses an integrated circuit (IC) chip including a piezoelectric device 3 that surrounds an opening extending through a substrate (see figs. 2a-3), in the same field of endeavor, for the purpose of using a ring-shaped piezoelectric actuator to deflect a circular shaped membrane.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to further modify Udayakumar, in view of Bakke, such that the piezoelectric device 240 has a ring-shaped top geometry that surrounds an opening extending through the substrate 202 as claimed. A practitioner in the art would have been motivated to do this for the purpose of using a single ring-shaped piezoelectric actuator to deflect a membrane, rather than using a plurality of piezoelectric elements 1408 as taught by Udayakumar in the embodiment of fig. 14.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. (US 8,723,241) considered with Wang (US 7,910,968), as applied to claim 8 above, in further view of Aleksov et al. (US 2019/0025573).
Udayakumar, as modified and applied to claim 8 above, discloses the invention as claimed, including that the pad 246 and the via 244 comprise a metal (see Udayakumar, col. 9, lines 11-23) and that the barrier layer comprises aluminum oxide (see Udayakumar, col. 5, lines 48-49), but fails to specifically teach that the metal of the pad 246 and the via 244 is aluminum. Aleksov discloses an integrated circuit (IC) chip including a piezoelectric device 730, pads 708, conductive traces 707, and vias 706, wherein the pads 708, conductive traces 707, and vias 706 comprise aluminum, in the same field of endeavor, for the purpose of using well known and inexpensive metal for the pads, conductive traces, and vias of the IC chip (see fig. 7A, and para. 0057).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to further modify Udayakumar, in view of Aleksov, such that the metal of the pad 246 and the via 244 is aluminum. A practitioner in the art would have been motivated to do this for the purpose of using well known and inexpensive metal for the pads 246 and vias 244 of the IC chip
Claims 6, 7, 10, 13, 23, 24, and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen discloses a piezoelectric device with a hydrogen getter layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL W HUBER whose telephone number is (571)272-7588.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Duc Nguyen, can be reached at telephone number 571-272-7503. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL W HUBER/Primary Examiner, Art Unit 2691
pwh
March 30, 2026