Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20220246180 A1).
Regarding independent claim 16, Lee discloses a semiconductor memory device (Fig. 15) comprising:
a cell array structure (CS without 100; [0122]: “cell array structure”) on a first substrate (100; [0122]: “substrate”); and
a peripheral circuit structure (PS) bonded (directly “bonded”) to the cell array structure,
wherein the cell array structure comprises:
a capacitor (DSP; [0126]: “capacitor”) on (indirectly “on”) the first substrate;
a vertical channel transistor ([0068]: “vertical channel transistors”) above (See annotated figure for “above” direction designation) the capacitor and electrically connected ([0072]: “electrically and respectively connected”) to the capacitor through contact patterns (LP); and
a first wiring structure (CCL) above the vertical channel transistor and electrically connected to the vertical channel transistor through a bit line (BL; [0122]: “bit lines”),
wherein the vertical channel transistor comprises:
active patterns (AP1/AP2) located above the first substrate in a vertical direction (See annotated figure for “vertical” direction designation) and separated from each other (Fig. 15 shows Ap1/AP2 are separate and distinct without any direct contact, thus they are “separated”) in a first horizontal direction (into/out-of the page. Note: “separated” is shown in top-down view in Fig. 6: D2, which shows AP1/AP2 do not directly contact each other in the D2 direction) and a second horizontal direction (See annotated figures 15 for 2nd direction designation. Note: this direction corresponds to Fig. 6: D1); and
first source/drain regions (Fig. 5: a portion of HP1/HP2; [0052]: “a first source/drain region”; [0053]: “a third source/drain region”) and second source/drain regions (Fig. 5: a portion of VP1/VP2; [0052]: “the uppermost end of the first vertical portion VP1 may be used as a second source/drain region”; [0053]: “the uppermost end of the second vertical portion VP2 may be used as a fourth source/drain region”) on (“on” in the above direction) and beneath (See annotated Fig. 5 for “beneath” direction designation) the active patterns, respectively, the first source/drain regions being in contact with and electrically connected to the bit line (direct “contact” and “connected” is illustrated) without a dopant source layer therebetween (there is no mention of a dopant source layer in the written specification, and the figures do not illustrate any auxiliary layer that would reasonably be designated as such), and the second source/drain regions being electrically connected to the capacitor through the contact patterns in contact with the second source/drain regions (this “connected” configuration is illustrated without any intervening structures) without a dopant source layer therebetween (there is no mention of a dopant source layer in the written specification, and the figures do not illustrate any auxiliary layer that would reasonably be designated as such), and
wherein the peripheral circuit structure comprises:
a peripheral circuit transistor (Fig. 15: SA; [0118]: “peripheral circuits SA…transistors” with [0133]: “integrated on the second semiconductor substrate 200”) beneath (See annotated Fig. 5 for “beneath” direction designation) a second substrate (200); and
a second wiring structure (PCL) beneath the peripheral circuit transistor and bonded to the first wiring structure.
Illustrated below is a marked and annotated figures of Fig. 5 and Fig. 15 of Lee.
PNG
media_image1.png
426
744
media_image1.png
Greyscale
PNG
media_image2.png
474
500
media_image2.png
Greyscale
Lee discloses the semiconductor memory device of claim 16 (Fig. 15), further comprising: a first bonding insulating layer (ML) on the first substrate; and a second bonding insulating layer (110) beneath the capacitor, wherein the first bonding insulating layer is bonded to the second bonding insulating layer.
Regarding claim 20, Lee discloses the semiconductor memory device of claim 16 (Fig. 15), wherein the cell array structure further comprises a first bonding pad (LMP), the peripheral circuit structure further comprises a second bonding pad (UMP) opposite to the first bonding pad, and the first bonding pad is bonded (directly “bonded”) to the second bonding pad.
Regarding claim 21, Lee discloses the semiconductor memory device of claim 16 (Fig. 15), wherein the peripheral circuit structure further comprises: a through via (See annotated figure) electrically connected to the second wiring structure on the second substrate (directly “connected”); and an input/output pad (one of UMP) electrically connected to the through via.
Claims 1, 3-11, and 14-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 20250048622 A1, effectively filed 8/2/2023).
The applied reference has a common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Choi discloses a semiconductor memory device (Fig. 4) comprising:
a bit line (BL) extending above a substrate (271) in a second horizontal direction (D2);
first and second active patterns (Fig. 8: APD1 and APD2) beneath (See annotated Fig. 4 for direction designation) the bit line, each of the first and second active patterns having a first surface (above direction surface) in contact (direct “contact”) with the bit line without a dopant source layer therebetween (there is no mention of a dopant source layer in the written specification, and the figures do not illustrate any auxiliary layer that would reasonably be designated as such) and a second surface (below direction surface) opposite to the first surface in a vertical direction (D3) that is perpendicular to the substrate;
a back-gate electrode (BG) between the first and second active patterns and extending above the substrate in a first horizontal direction (D1, See top-down view in Fig. 2 showing “extending…in”) that is perpendicular to the second horizontal direction by crossing the bit line (perpendicular “crossing” is shown);
a first word line (WL1) extending in the first horizontal direction (D1, See top-down view in Fig. 2 showing “extending…in”) at one side of the first active pattern (one D2 side);
a second word line (WL2) extending in the first horizontal direction (D1, See top-down view in Fig. 2 showing “extending…in”) at an opposite side of the second active pattern (the other D2 side); and
contact patterns (Fig. 4: BC) in contact (direct “contact”) with the second surfaces of the first and second active patterns,
wherein the first and second active patterns comprise first source/drain regions adjacent to the bit line ([0079]: “first dopant region adjacent to the bit line”), second source/drain regions adjacent to the contact patterns ([0079]: “second dopant region adjacent to the contact pattern”), and channel regions between the first source/drain regions and the second source/drain regions ([0079]: “channel region between the first dopant region and the second dopant region”).
Illustrated below are marked and annotated figures of Fig. 4 and Fig. 8 of Choi.
PNG
media_image3.png
552
597
media_image3.png
Greyscale
PNG
media_image4.png
458
389
media_image4.png
Greyscale
Regarding claim 3, Choi discloses the semiconductor memory device of claim 1 (Fig. 4), wherein the first and second active patterns include a monocrystalline semiconductor material ([0204]: “monocrystalline silicon”).
Regarding claim 4, Choi discloses the semiconductor memory device of claim 1 (Fig. 2), wherein each of the first and second active patterns has a width (D1 width) greater than a width of the bit line in the first horizontal direction (AP1/AP2 each extend in the d1 direction beyond the footprint of BL).
Regarding claim 5, Choi discloses the semiconductor memory device of claim 1 (Fig. 2), wherein each of the first and second active patterns has a uniform width in the second horizontal direction (D2 width appears straight, and therefore “uniform”), and wherein each of the contact patterns is wider (BC extends beyond AP1/AP2 each way in the D2 direction, and is therefore “wider”) in the second horizontal direction than the uniform width.
Regarding claim 6, Choi discloses the semiconductor memory device of claim 1 (Fig. 8), wherein each of the first and second word lines and the back-gate electrode has an upper surface (See annotated figure for “upper” direction designation) close to the bit line and a lower surface (See annotated figure for “lower” direction designation) close to the contact patterns, and the lower surfaces of the first and second word lines are at a different level (designating the D2 direction as the “level”) from a level of the lower surface of the back-gate electrode (these structures are positioned differently along the D2 direction and thus have different levels along the D2 direction).
Regarding claim 7, Choi discloses the semiconductor memory device of claim 1 (Fig. 8), wherein each of the first and second word lines and the back-gate electrode has a length in the vertical direction, and the lengths of the first and second word lines are different from the length of the back-gate electrode (“different” because back-gate BG has a curved surface, and therefore must have a least some length that differs from the corresponding length of the word lines WL1/WL2).
Regarding claim 8, Choi discloses the semiconductor memory device of claim 1 (Fig. 8), further comprising gate insulating patterns (GOX) between the first and second active patterns and the first and second word lines.
Regarding claim 9, Choi discloses the semiconductor memory device of claim 8 (Fig. 8), further comprising a second insulating pattern (111/113) between the first and second word lines and between the gate insulating patterns.
Regarding claim 10, Choi discloses the semiconductor memory device of claim 1, further comprising a first insulating pattern (111/113) between the first and second active patterns adjacent to each other in the second horizontal direction and between the second source/drain regions.
Regarding independent claim 11, Choi discloses a semiconductor memory device (Fig. 4) comprising:
a bit line (BL) extending above a substrate (271) in a second horizontal direction (D2);
first and second active patterns (Fig. 8: APD1 and APD2) alternating with each other in the second horizontal direction (Fig. 2 shows sufficient duplication to teach “alternating”) beneath the bit line (See annotated Fig. 4 for direction designation), each of the first and second active patterns having a first surface (above direction surface) in contact (direct “contact”) with the bit line without a dopant source layer therebetween (there is no mention of a dopant source layer in the written specification, and the figures do not illustrate any auxiliary layer that would reasonably be designated as such) and a second surface (below direction surface) opposite to the first surface in a vertical direction (D3) that is perpendicular to the substrate;
a back-gate electrode (BG) between the first and second active patterns and extending above the substrate in a first horizontal direction (D1, See top-down view in Fig. 2 showing “extending…in”) that is perpendicular to the second horizontal direction by crossing the bit line (perpendicular “crossing” is shown);
a first word line (WL1) extending in the first horizontal direction (D1, See top-down view in Fig. 2 showing “extending…in”) at one side of the first active pattern (one D2 side);
a second word line (WL2) extending in the first horizontal direction (D1, See top-down view in Fig. 2 showing “extending…in”) at an opposite side of the second active pattern (the other D2 side);
gate insulating patterns (GOX) between the first and second active patterns and the first and second word lines; and
contact patterns (Fig. 4: BC) in contact (direct “contact”) with the second surfaces of the first and second active patterns without a dopant source layer therebetween (there is no mention of a dopant source layer in the written specification, and the figures do not illustrate any auxiliary layer that would reasonably be designated as such) and a second surface (below direction surface),
wherein the first and second active patterns comprise first source/drain regions adjacent to the bit line ([0079]: “first dopant region adjacent to the bit line”), second source/drain regions adjacent to the contact patterns ([0079]: “second dopant region adjacent to the contact pattern”), and channel regions between the first source/drain regions and the second source/drain regions ([0079]: “channel region between the first dopant region and the second dopant region”).
Regarding claim 14, Choi discloses the semiconductor memory device of claim 11 (Fig. 8), wherein each of the first and second active patterns have a first side surface (one D2 side) and a second side surface (the other D2 side) opposite to each other in the second horizontal direction, wherein the first word line is adjacent to the first side surface (“adjacent” in the D2 direction), and wherein the second word line is adjacent to the second side surface (“adjacent” in the D2 direction).
Regarding claim 15, Choi discloses the semiconductor memory device of claim 11 (Fig. 4), further comprising a capacitor (DSP; [0161]: “capacitor”) on the contact patterns.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 16 above, and further in view of Yoon (US 20220223734 A1).
Regarding claim 18, Lee discloses the semiconductor memory device of claim 16 (Fig. 15), but fails to teach any specific configuration for the source/drain region “doping concentration”. Thus, Lee fails to teach “wherein the second source/drain regions have a constant doping concentration in the vertical direction that is perpendicular to the first substrate”.
Yoon discloses wherein the second source/drain regions (Fig. 2: 130 or 110) have a constant doping concentration (See the concentration graph of Fig. 2) in the vertical direction (height direction) that is perpendicular to the first substrate (Fig. 3E: 11). Modifying the device (of Lee) by substituting the vertical channel transistors (of Yoon) in place of the vertical channel transistors would arrive at the claimed “constant doping concentration” configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a vertical channel transistor is used (Lee: [0068]: “vertical channel transistors”; Yoon: [0024]: “vertical channel”). Yoon provides a teaching to motivate one of ordinary skill in the art before the effective filing date to use the claimed configuration in that it would enhance operational characteristics of the device ([0008]: “leakage current may be reduced”; [0009]: “contact resistance may be enhanced”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed concentration configuration because it would enhance operational characteristics of the device. MPEP 2143 (I)(G).
Illustrated below is Fig. 2 of Yoon.
PNG
media_image5.png
402
464
media_image5.png
Greyscale
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 1 above, and further in view of Yoon.
Regarding claim 2, Choi discloses the semiconductor memory device of claim 1, but fails to teach any specific configuration for the source/drain region “doping concentration”. Thus, Choi fails to teach “wherein the first source/drain regions have a constant doping concentration in the vertical direction that is perpendicular to the substrate”.
Yoon discloses wherein the first source/drain regions (Fig. 2: 130 or 110) have a constant doping concentration (See the concentration graph of Fig. 2) in the vertical direction (height direction) that is perpendicular to the first substrate (Fig. 3E: 11). Modifying the device (of Choi) by substituting the source/drain regions (of Yoon) in place of the source/drain regions would arrive at the claimed “constant doping concentration” configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a vertical channel transistor is used (Choi: [0002]: “vertical channel transistor”; Yoon: [0024]: “vertical channel”). Yoon provides a teaching to motivate one of ordinary skill in the art before the effective filing date to use the claimed configuration in that it would enhance operational characteristics of the device ([0008]: “leakage current may be reduced”; [0009]: “contact resistance may be enhanced”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed concentration configuration because it would enhance operational characteristics of the device. MPEP 2143 (I)(G).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 11 above, and further in view of Yoon.
Regarding claim 12, Choi discloses the semiconductor memory device of claim 11, but fails to teach any specific configuration for the source/drain region “doping concentration”. Thus, Choi fails to teach “wherein the first source/drain regions have a constant doping concentration in the vertical direction that is perpendicular to the substrate”.
Yoon discloses wherein the first source/drain regions (Fig. 2: 130 or 110) have a constant doping concentration (See the concentration graph of Fig. 2) in the vertical direction (height direction) that is perpendicular to the first substrate (Fig. 3E: 11). Modifying the device (of Choi) by substituting the source/drain regions (of Yoon) in place of the source/drain regions would arrive at the claimed “constant doping concentration” configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a vertical channel transistor is used (Choi: [0002]: “vertical channel transistor”; Yoon: [0024]: “vertical channel”). Yoon provides a teaching to motivate one of ordinary skill in the art before the effective filing date to use the claimed configuration in that it would enhance operational characteristics of the device ([0008]: “leakage current may be reduced”; [0009]: “contact resistance may be enhanced”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed concentration configuration because it would enhance operational characteristics of the device. MPEP 2143 (I)(G).
Regarding claim 13, Choi discloses the semiconductor memory device of claim 11, but fails to teach any specific configuration for the source/drain region “doping concentration”. Thus, Choi fails to teach “wherein the second source/drain regions have a constant doping concentration in the vertical direction that is perpendicular to the substrate”.
Yoon discloses wherein the second source/drain regions (Fig. 2: 130 or 110) have a constant doping concentration (See the concentration graph of Fig. 2) in the vertical direction (height direction) that is perpendicular to the first substrate (Fig. 3E: 11). Modifying the device (of Choi) by substituting the source/drain regions (of Yoon) in place of the source/drain regions would arrive at the claimed “constant doping concentration” configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a vertical channel transistor is used (Choi: [0002]: “vertical channel transistor”; Yoon: [0024]: “vertical channel”). Yoon provides a teaching to motivate one of ordinary skill in the art before the effective filing date to use the claimed configuration in that it would enhance operational characteristics of the device ([0008]: “leakage current may be reduced”; [0009]: “contact resistance may be enhanced”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed concentration configuration because it would enhance operational characteristics of the device. MPEP 2143 (I)(G).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oh (US 20250081514 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Yoo (US 20250107066 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Kim (US 20240147706 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Lee (US 20240147701 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Jeong (US 20230320077 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Lee (US 20230363143 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Lee (US 20240023311 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Lee (US 20230371243 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Park (US 20250132253 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Lee (US 20240334677 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Jeong (US 20240130108 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Choi (US 20240098984 A1) discloses a substantially similar semiconductor memory device with a back-gate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
Prosecution Insights