DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,996,369. Although the claims at issue are not identical, they are not patentably distinct from each other because applicant merely seeks to broaden the claims by removing exposure of a vertical port by an aperture and introducing a cover from the dependent claims. The claims of the instant application are fully encompassed by the scope of US11966369, and the allowable subject matter remains.
2. An electronic device, comprising:
a substrate comprising a dielectric structure and a conductive structure, a top side and a bottom side, wherein the substrate has a cavity extending from the top side of the substrate to the bottom side of the substrate
an electronic component coupled to the conductive structure and overlapping the cavity at the bottom side of the substrate
a vertical interconnect coupled to the conductive structure at the bottom side of the substrate
a cover over the top side of the substrate and covering the cavity
an encapsulant at the bottom side of the substrate and covering a lateral side of the electronic component and surrounding the vertical interconnect
1. An electronic device, comprising:
a first substrate comprising a first conductive structure
a first electronic component coupled to a bottom side of the first substrate
a vertical interconnect coupled to the bottom side of the first substrate and located external to the first electronic component
an encapsulant covering the vertical interconnect, a first lateral side of the first electronic component, and at least a portion of the bottom side of the first substrate
wherein a vertical port on the first electronic component is exposed by an aperture of the first substrate
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-22 of U.S. Patent No. 11,482,496. Although the claims at issue are not identical, they are not patentably distinct from each other because applicant merely seeks to broaden the claims by removing exposure of a vertical port by an aperture. The claims of the instant application are fully encompassed by the scope of US11966369, and the allowable subject matter remains.
2. An electronic device, comprising:
a substrate comprising a dielectric structure and a conductive structure, a top side and a bottom side, wherein the substrate has a cavity extending from the top side of the substrate to the bottom side of the substrate
an electronic component coupled to the conductive structure and overlapping the cavity at the bottom side of the substrate
a vertical interconnect coupled to the conductive structure at the bottom side of the substrate
a cover over the top side of the substrate and covering the cavity
an encapsulant at the bottom side of the substrate and covering a lateral side of the electronic component and surrounding the vertical interconnect
1. An electronic device, comprising:
a first substrate comprising a first conductive structure
a second substrate comprising a second conductive structure, wherein the first substrate is over the second substrate
a first electronic component between the first substrate and the second substrate
a vertical interconnect between the first substrate and the second substrate, wherein the vertical interconnect is coupled with the first conductive structure and the second conductive structure, and the vertical interconnect is external to the first electronic component
an encapsulant between the first substrate and the second substrate covering the vertical interconnect and contacting the vertical interconnect
wherein a vertical port on the first electronic component is exposed by an aperture of the first substrate
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/N.R.P/ 7/31/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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