CTNF 18/675,463 CTNF 90499 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 7, 9-14, and 17 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Izumi et al. (U.S. Patent No. 7,800,163) . Regarding to claim 1, Izumi teaches a semiconductor device (Figs. 14-16), comprising: a gate stacking structure, the gate stacking structure including a plurality of interlayer insulation layers (Fig. 14B, elements 611/613 ) and a plurality of gate electrodes (Fig. 14B, elements 612/614 ) alternately stacked with each other on a substrate (Fig. 14B, element 200 ), the plurality of gate electrodes including a selection gate electrode (column 10, lines 22-24); a plurality of channel structures extending in a direction crossing the substrate such that the plurality of channel structures penetrate the gate stacking structure (Fig. 14B, channel structure in the trench, only one shown in the figure, however, there are plurality of channel structures are formed according to the circuit shown in Fig 2 ), each of the plurality of channel structures including a gate dielectric layer and a channel layer (Fig. 14B, gate dielectric layer 617 and channel layer 621/623/624 ); and at least one separation pattern separating the selection gate electrode at one surface of the gate stacking structure (Fig. 14B, element 618 ), wherein the plurality of channel structures includes an adjacent channel structure adjacent to the at least one separation pattern, the adjacent channel structure includes a first portion having an adjacent surface adjacent to the separation pattern and having a separation surface spaced apart from the separation pattern (Fig. 14B, element 619 , first adjacent surface adjacent facing the separation pattern 618 , separation surface facing layer 620 ), and at least one of the gate dielectric layer or the channel layer, in the first portion of the adjacent channel structure, is on the separation surface and the adjacent surface (Fig. 14B, channel layer including portions 621 , 623 , and 624 , in the first portion of the adjacent channel structure 619 , is on the separation surface and above the adjacent surface ). Regarding to claim 2, Izumi teaches in a plan view, the gate dielectric layer and the channel layer are continuously and entirely disposed in the first portion such that the gate dielectric and the channel layer do not have a cut surface (Fig. 14B). Regarding to claim 3, Izumi teaches the adjacent channel structure further includes a second portion other than the first portion, and in a cross-sectional view, the gate dielectric layer and the channel layer are continuously and entirely disposed in the first portion and the second portion such that the gate dielectric layer and the channel layer do not have a cut surface (Fig. 14B). Regarding to claim 4, Izumi teaches in the first portion, the gate dielectric layer includes a first dielectric portion on the separation surf ace, and a second dielectric portion connected to the first dielectric portion on the adjacent surface, and in the first portion, the channel layer includes a first channel portion on the first dielectric portion on the separation surface, and a second channel portion connected to the first channel portion on the second dielectric portion on the adjacent surface (Fig. 14B). Regarding to claim 7, Izumi teaches at least one of an area of the first dielectric portion is greater than an area of the second dielectric portion or an area of the first channel portion is greater than an area of the second channel portion (Fig. 14B). Regarding to claim 9, Izumi teaches the separation surface of the first portion has a rounded surface, and the adjacent surf ace of the first portion has a planar surface, a rounded surface having a curvature less than a curvature of the separation surface, or a curvature having a curvature direction opposite to a curvature direction of the separation surface (Fig. 14B). Regarding to claim 10, Izumi teaches the first portion further includes at least one of a core insulation layer surrounded by the channel layer, or a channel pad on at least one of the channel layer or the core insulation layer, and the at least one of the core insulation layer or the channel pad in the first portion is entirely spaced apart from the separation pattern (Fig. 14B, element 625 ). Regarding to claim 11, Izumi teaches the adjacent channel structure includes a second portion, the adjacent channel structure further includes a core insulation layer surrounded by the channel layer (Fig. 14B, element 625 ), and in a plan view, a stacking order of the gate dielectric layer, the channel layer, and the core insulation layer in the first portion is the same as a stacking order of the gate dielectric layer, the channel layer, and the core insulation layer in the second portion (Fig. 14B). Regarding to claim 12, Izumi teaches the plurality of channel structures further include at least one separation channel structure spaced apart from the separation pattern, the at least one separation channel structure having a planar shape different from a planar shape of the first portion of the adjacent channel structure (Fig. 14B). Regarding to claim 13, Izumi teaches the adjacent channel structure and the separation channel structure each further include at least one of a core insulation layer surrounded by the channel layer or a channel pad on at least one of the channel layer or the core insulation layer (Fig. 14B, element 625 ), and in a plan view, a stacking order of the gate dielectric layer, the channel layer, and the core insulation layer in the adjacent channel structure is the same as a stacking order of the gate dielectric layer, the channel layer, and the core insulation layer in the at least one separation channel structure, or a stacking order of the gate dielectric layer, the channel layer, and the channel pad in the adjacent channel structure is the same as a stacking order of the gate dielectric layer, the channel layer, and the channel pad in the at least one separation channel structure (Fig. 14B). Regarding to claim 14, Izumi teaches the separation pattern includes an insulating separation pattern (Fig. 14B), or the separation pattern includes a spacer layer and a conductive layer inside the spacer layer. Regarding to claim 17, Izumi teaches an electronic system, comprising: a main substrate (Fig. 14B, element 100 ); a semiconductor device on the main substrate (Fig. 14B, transistor include S/D 102 ); and a controller electrically connected to the semiconductor device on the main board (Fig. 14B, element 200a ), wherein the semiconductor device includes a gate stacking structure, the gate stacking structure including a plurality of interlayer insulation layers (Fig. 14B, elements 611/613 ) and a plurality of gate electrodes (Fig. 14B, elements 612/614 ) alternately stacked with each other on a substrate (Fig. 14B, element 200 ), the plurality of gate electrodes including a selection gate electrode (column 10, lines 22-24); a plurality of channel structures extending in a direction crossing the substrate such that the plurality of channel structures penetrate the gate stacking structure (Fig. 14B, channel structure in the trench, only one shown in the figure, however, there are plurality of channel structures are formed according to the circuit shown in Fig 2 ), each of the plurality of channel structures including a gate dielectric layer and a channel layer (Fig. 14B, gate dielectric layer 617 and channel layer 621/623/624 ); and at least one separation pattern separating the selection gate electrode at one surface of the gate stacking structure (Fig. 14B, element 618 ), wherein the plurality of channel structures includes an adjacent channel structure adjacent to the at least one separation pattern, the adjacent channel structure includes a first portion having an adjacent surface adjacent to the separation pattern and having a separation surface spaced apart from the separation pattern (Fig. 14B, element 619 , first adjacent surface adjacent facing the separation pattern 618 , separation surface facing layer 620 ), and at least one of the gate dielectric layer or the channel layer, in the first portion of the adjacent channel structure, is on the separation surface and the adjacent surface (Fig. 14B, channel layer including portions 621 , 623 , and 624 , in the first portion of the adjacent channel structure 619, is on the separation surface and above the adjacent surface ) . 07-15-03-aia AIA Claim 18 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Howder et al. (U.S. Patent No. 11,737,275) . Regarding to claim 18, Howder teaches a manufacturing method of a semiconductor device, comprising: forming a stacking structure (Fig. 2, stack 52/54/56 ); forming a plurality of preliminary channel structures penetrating the stacking structure (Fig. 2, elements 58/60 ); forming a separation pattern by forming an opening for the separation pattern to overlap at least one of the plurality of preliminary channel structures (Figs. 3-5, element 70 ) and filling at least a partial portion of the opening for the separation pattern with an insulating material (Fig. 6, element 78 ); and removing the plurality of preliminary channel structures (Figs. 8-11) and forming a plurality of channel structures (Figs. 12-13). Allowable Subject Matter Claims 5-6, 8, 15-16, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding to claim 5, the prior art fails to anticipate or render obvious the claimed limitations including “at least one of the connected first dielectric and second dielectric portions have an asymmetric shape or the connected first channel and second channel portions have an asymmetric shape” in combination with the limitations recited in claims 1 and 4. Regarding to claim 6, the prior art fails to anticipate or render obvious the claimed limitations including “at least one of the second dielectric portion or the second channel portion has a shape different from the partially annular shape” in combination with the limitations recited in claims 1 and 4, and the rest of limitations recited in claim 6. Regarding to claim 8, the prior art fails to anticipate or render obvious the claimed limitations including “the adjacent channel structure further includes a second portion, a dielectric portion of the gate dielectric layer in the second portion is connected to the first dielectric portion and the second dielectric portion of the gate dielectric layer in the first portion, and a channel portion of the channel layer in the second portion is connected to the first channel portion and the second channel portion of the channel layer in the first portion” in combination with the limitations recited in claims 1 and 4. Regarding to claim 15, the prior art fails to anticipate or render obvious the claimed limitations including “the separation pattern is adjacent to the selection channel structure of the adjacent channel structure such that the selection channel structure of the adjacent channel structure constitutes the first portion of the adjacent channel structure” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 15. Regarding to claim 19, the prior art fails to anticipate or render obvious the claimed limitations including “the plurality of channel structures include an adjacent channel structure, the adjacent channel structure including an adjacent surface adjacent to the separation pattern and a separation surf ace spaced apart from the separation pattern, and the forming of the plurality of channel structures includes forming a gate dielectric layer and a channel layer on the adjacent surface adjacent to the separation pattern in the adjacent channel structure” in combination with the limitations recited in claim 18. Pertinent Art For the benefits of the Applicant, US-8437192-B2, US-20240389327-A1, US-11296110-B2, US-11508744-B2, US-8148789-B2US-9831257-B2, US-12302560-B2, US-20240196613-A1, US-9129857-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose the combination of limitations including “the plurality of channel structures includes an adjacent channel structure adjacent to the at least one separation pattern, the adjacent channel structure includes a first portion having an adjacent surface adjacent to the separation pattern and having a separation surface spaced apart from the separation pattern, and at least one of the gate dielectric layer or the channel layer, in the first portion of the adjacent channel structure, is on the separation surface and the adjacent surface.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VU A VU/Primary Examiner, Art Unit 2897 Application/Control Number: 18/675,463 Page 2 Art Unit: 2897 Application/Control Number: 18/675,463 Page 4 Art Unit: 2897 Application/Control Number: 18/675,463 Page 5 Art Unit: 2897 Application/Control Number: 18/675,463 Page 6 Art Unit: 2897 Application/Control Number: 18/675,463 Page 7 Art Unit: 2897 Application/Control Number: 18/675,463 Page 8 Art Unit: 2897 Application/Control Number: 18/675,463 Page 9 Art Unit: 2897 Application/Control Number: 18/675,463 Page 10 Art Unit: 2897 Application/Control Number: 18/675,463 Page 11 Art Unit: 2897
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