Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9-11, 17, 23-32 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US Pub # 2019/0333554).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Ma et al. teach a memory chip comprising: a delay amount adjustment circuit configured to change a logic level combination of a code signal that adjusts a first delay amount for a strobe signal that is input or output through a conductive via based on a chip ID (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, Unit 220, 224 delay circuit change logic level of code signal En1 and adjust first delay amount shifts1 for 204 DQS strobe signal from specific bank / chip) and a test mode signal after a start of a post-training operation and configured to generate an op-code signal by performing an arithmetic operation on the code signal (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, Post training operation after step 412, op-code signal generated by inverting operation by 240 on the code signal En1); and a data processing circuit configured to delay the strobe signal by a second delay amount that is based on the op-code signal, configured to latch internal data in synchronization with the strobe signal that is delayed by the second delay amount, and configured to output, as data, the internal data that are latched (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048, 0056-0057, Unit 216x are latch, shift control logic unit 632 delay strobe signal DQS by second delay amount shifts2 based on op-code signal En2, output internal data by latch unit 216x).
Even though Ma et al. teach adjusting delay amount for the signal but silent exclusively about arithmetic operation. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Ma et al. where En2 op-code was generated based on an arithmetic operation of code signal En1 in order to properly control delay amount and minimize or eliminate multiple strobe signal training procedures (see paragraph 0004).
Regarding claim 2, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ma et al. further teach, wherein: the first delay amount is a delay amount of a replica delay circuit, and the second delay amount is a delay amount of the conductive via (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0045).
Regarding claim 3, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ma et al. further teach, wherein the code signal is a signal that is generated to adjust the delay amount for the strobe signal through a replica delay circuit having a delay amount for the conductive via after a start of a pre-training operation that is performed before the post-training operation is performed (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048, 0056).
Regarding independent claim 9, Ma et al. teach a semiconductor chip comprising: a first memory chip configured to generate a first op-code signal by performing an arithmetic operation on a first code signal that adjusts a delay amount for a strobe signal that is input through a first conductive via when a chip identification (ID) is at a first logic level combination after a start of a post-training operation (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, Unit 220, 224 delay circuit, 204 DQS strobe signal, bank ID is chip ID) and configured to output first data through a second conductive via by delaying the strobe signal by a delay amount that is adjusted based on the first op-code signal; and a second memory chip configured to generate a second op-code signal by performing an arithmetic operation on a second code signal that adjusts the delay amount for the strobe signal that is input through the first conductive via when the chip ID is at a second logic level combination after the start of the post-training operation (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, Post training operation after step 412), and configured to output second data through a third conductive via by delaying the strobe signal by a delay amount that is adjusted based on the second op-code signal latched (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048, 0056-0057, Unit 216x are latch, shift control logic unit 632 delay strobe signal DQS).
Even though Ma et al. teach adjusting delay amount for the signal but silent exclusively about arithmetic operation. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Ma et al. where En2 op-code was generated based on an arithmetic operation of code signal En1 in order to properly control delay amount and minimize or eliminate multiple strobe signal training procedures (see paragraph 0004).
Regarding claim 10, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Ma et al. further teach, wherein the second memory chip is stacked over the first memory chip and the first through third conductive vias (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0040).
Regarding claim 11, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Ma et al. further teach, wherein the first memory chip comprises: a first delay amount adjustment circuit configured to change a logic level combination of the first code signal based on a test mode signal when the chip ID is at the first logic level combination after the start of the post-training operation and configured to generate the first op-code signal by performing an arithmetic operation on the first code signal (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0042); and a first data processing circuit configured to delay the strobe signal by a second delay amount that is based on the first op-code signal, configured to latch first internal data in synchronization with the strobe signal that is delayed, and configured to output, as the first data, the first internal data that are latched through the second conductive via (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048, 0056).
Regarding claim 17, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Ma et al. further teach, wherein the second memory chip comprises: a second delay amount adjustment circuit configured to change a logic level combination of the second code signal based on a test mode signal when the chip ID is at the second logic level combination after the start of the post-training operation (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0045) and configured to generate a second op-code signal by performing an arithmetic operation on the second code signal; and a second data processing circuit configured to delay the strobe signal by a second delay amount that is based on the second op-code signal, configured to latch second internal data in synchronization with the strobe signal that is delayed, and configured to output, as the second data, the second internal data that are latched through the third conductive via (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048).
Regarding independent claim 23, Ma et al. teach a semiconductor chip comprising: a first memory chip, associated with a first chip identification (ID), configured to, in response to receiving the first chip ID, generate a first op-code signal by performing an arithmetic operation on a first code signal that adjusts a delay amount for a strobe signal that is input through a first signal path (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, Unit 220, 224 delay circuit, 204 DQS strobe signal, bank ID is chip ID) and adjust the delay amount for the strobe signal based on the first op-code signal; and a second memory chip, associated with a second chip identification (ID), configured to, in response to receiving the second chip ID, generate a second op-code signal by performing an arithmetic operation on a second code signal that adjusts the delay amount for the strobe signal that is input through a second signal path latched (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0025) and adjust the delay amount for the strobe signal based on the second op-code signal latched (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048, 0056-0057, Unit 216x are latch, shift control logic unit 632 delay strobe signal DQS).
Even though Ma et al. teach adjusting delay amount for the signal but silent exclusively about arithmetic operation. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Ma et al. where En2 op-code was generated based on an arithmetic operation of code signal En1 in order to properly control delay amount and minimize or eliminate multiple strobe signal training procedures (see paragraph 0004).
Regarding claim 24, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 23 on which this claim depends.
Ma et al. further teach, wherein the first and second signal paths are implemented with a plurality of conductive vias or a plurality of segments of wire bonding (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048).
Regarding claim 25, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 23 on which this claim depends.
Ma et al. further teach, wherein the first memory chip and the second memory chip are stacked over the first signal path and the second signal path (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039).
Regarding claim 26, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 23 on which this claim depends.
Ma et al. further teach, wherein: the first memory chip adjusts the delay amount for the strobe signal when the chip ID is at a first logic level combination, and the second memory chip adjusts the delay amount for the strobe signal when the chip ID is at a second logic level combination (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0040).
Regarding claim 27, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 23 on which this claim depends.
Ma et al. further teach, wherein the first memory chip comprises: a first delay amount adjustment circuit configured to change a logic level combination of the first code signal that adjusts the first delay amount of the strobe signal based on the chip ID and a test mode signal and configured to generate the first op-code signal by performing an arithmetic operation on the first code signal (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0043); and a first data processing circuit configured to delay the strobe signal by a second delay amount that is based on the first op-code signal, configured to latch first internal data in synchronization with the strobe signal that is delayed by the second delay amount, and configured to output, as first data, the first internal data that are latched through the first signal path (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048, 0056-0057).
Regarding claim 28, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 27 on which this claim depends.
Ma et al. further teach, wherein: the first delay amount is a delay amount for a first replica delay circuit, and the second delay amount is a delay amount for the first signal path (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031).
Regarding claim 29, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 23 on which this claim depends.
Ma et al. further teach, wherein the second memory chip comprises: a second delay amount adjustment circuit configured to change a logic level combination of the second code signal that adjusts a third delay amount for the strobe signal based on the chip ID and a test mode signal and configured to generate the second op-code signal by performing an arithmetic operation on the second code signal (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039); and a second data processing circuit configured to delay the strobe signal by a fourth delay amount that is based on the second op-code signal, configured to latch second internal data in synchronization with the strobe signal that is delayed by the fourth delay amount, and configured to output, as second data, the second internal data that are latched through the second signal path (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0047).
Regarding claim 30, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 29 on which this claim depends.
Ma et al. further teach, wherein: the third delay amount is a delay amount for a second replica delay circuit, and the fourth delay amount is a delay amount for the second signal path (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048).
Regarding independent claim 31, Ma et al. teach a method comprising: generating an op-code signal by performing an arithmetic operation on a code signal that adjusts a delay amount for a strobe signal (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, Unit 220, 224 delay circuit, 204 DQS strobe signal); adjusting the delay amount for the strobe signal based on the op-code signal; delaying the strobe signal by the adjusted delay amount; latching internal data in synchronization with the strobe signal that is delayed by the adjusted delay amount; and outputting the latched internal data latched (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031, 0039-0048, 0056-0057, Unit 216x are latch, shift control logic unit 632 delay strobe signal DQS).
Even though Ma et al. teach adjusting delay amount for the signal but silent exclusively about arithmetic operation. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Ma et al. where shift1 / shift2 were used to calculate actual delay amount by the control circuitry i.e. an arithmetic operation is done for the delay calculation in order to minimize or eliminate multiple strobe signal training procedures (see paragraph 0004).
Regarding claim 32, Ma et al. teach all claimed subject matter as applied in prior rejection of claim 31 on which this claim depends.
Ma et al. further teach, wherein the adjusted delay amount is based on a signal path for the strobe signal (see Fig. 1-4, 6 and paragraph 0014-0018, 0020-0031).
Allowable Subject Matter
Claims 4-8, 12-16, 18-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the delay amount adjustment circuit comprises: a replica delay circuit configured to generate a transfer strobe signal by delaying the strobe signal by the first delay amount that is adjusted based on the code signal; a code signal generation circuit configured to adjust a logic level combination of the code signal by comparing phases of the strobe signal and the transfer strobe signal; a training control circuit configured to generate an operation enable signal that is enabled when the chip ID is at a preset logic level combination; and a training circuit configured to change the logic level combination of the code signal based on the test mode signal when the operation enable signal is enabled and configured to generate the op-code signal by performing an arithmetic operation on the code signal.
Claim 12 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the first delay amount adjustment circuit comprises: a first replica delay circuit configured to generate a first transfer strobe signal by delaying the strobe signal by a first delay amount that is adjusted based on the first code signal; a first code signal generation circuit configured to adjust the logic level combination of the first code signal by comparing phases of the strobe signal and the first transfer strobe signal; a first training control circuit configured to generate a first operation enable signal that is enabled when the chip ID is at the first logic level combination; and a first training circuit configured to change the logic level combination of the first code signal based on the test mode signal when the first operation enable signal is enabled and configured to generate the first op-code signal by performing an arithmetic operation on the first code signal.
Claim 18 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the second delay amount adjustment circuit comprises: a second replica delay circuit configured to generate a second transfer strobe signal by delaying the strobe signal by a third delay amount that is adjusted based on the second code signal; a second code signal generation circuit configured to adjust the logic level combination of the second code signal by comparing phases of the strobe signal and the second transfer strobe signal; a second training control circuit configured to generate a second operation enable signal that is enabled when the chip ID has the second logic level combination; and a second training circuit configured to change the logic level combination of the second code signal based on the test mode signal when the second operation enable signal is enabled and configured to generate the second op-code signal by performing an arithmetic operation on the second code signal.
Response to Arguments
Applicant's arguments filed 05/19/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 16 of remarks) that Ma et al. do not disclose, "a delay amount adjustment circuit configured to change a logic level combination of a code signal that adjusts a first delay amount for a strobe signal that is input or output through a conductive via based on a chip ID". Examiner respectfully disagrees with this statement.
First, the limitation “Chip ID” is very broad as the limitation did not specify any specific size of the chip / package.
Also, the limitation “code signal” refers to any signal that control the delay amount for strobe signal.
In Fig.2, paragraph 0020-0031, Ma et al. teach the bank control logic unit select any / all bank (Bank0 to 7) using address (BA[2:0]). if the size of the whole chip /package taught by the applicant is same as Bank 0 or Bank 1 or …Bank 7 (as taught by Ma et al.), then each bank ID would be also called chip ID or package ID. When specific DQS are selected for delay operation, it must be selected for specific bank / chip/ die.
At least specially in Fig.2, Ma et al. teach first delay adjustment circuit (220 + 232) change logic level of code signal En1 and adjust first delay amount shifts1 for specific DQS strobe signal which is from specific Chip / Die/ bank / section / segment etc. i.e. chip ID automatically selected by the controller.
Applicant argues (see page 17 of remarks) that Ma fails to teach or suggest "to generate a first op-code signal by performing an arithmetic operation on a first code signal that adjusts a delay amount for a strobe signal that is input through a first conductive via when a chip identification (ID) is at a first logic level combination" and "delaying the strobe signal by a delay amount that is adjusted based on the first op-code signal" as set forth in claim 9.
At least specially in Fig.2, Ma et al. teach to generate opcode signal En2 based on arithmetic operation (inversion by 240) of code signal En1 and adjust second delay amount shifts2 by the second delay circuit 224 for strobe signal DQS.
Applicant further argues that Ma fails to teach or suggest "a first memory chip, associated with a first chip identification (ID)" and "a second memory chip, associated with a second chip identification (ID)" as set forth in independent claim 23.
As explained above, as the limitation is broad, bank ID of Ma et al. would be considered as chip ID as both can be same size.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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