DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 28, 2024, IDS filed on May 29, 2025 and IDS filed on August 4, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because in Figs. 7C-7E, the reference characters “52” and “60L” have both been used to designate an optional blocking dielectric layer.
The drawings are also objected to for the following informality: In Fig. 23, the reference character “4” should be corrected to be --5--. Support can be found at least in the paragraph [0131] of the original specification.
No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d) . If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 18-20 are objected to because of the following informalities:
In claim 18, line 2, “in layer contact via cavity” should read --in the layer contact via cavity--.
In claim 19, line 2, “in layer contact via cavity” should read --in the layer contact via cavity--.
In claim 20 lines 4-5, “vertical stack of memory elements” should read --a vertical stack of memory elements--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 15 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Costa et al. US 2018/0182771.
Regarding claim 1, Costa teaches a memory device (e.g., Fig. 16 and the description thereof; also see Figs. 1-15 pertaining to the manufacturing process for the device of Fig. 16 for additional details), comprising:
an alternating stack of insulating layers (e.g., 176, 232, Fig. 16; [166], [172]) and electrically conductive layers (e.g., 346, 246, Fig. 16; [224]), wherein the alternating stack comprises a staircase region (e.g., staircase region of 200, Fig. 16; Fig. 12) in which lateral extents of the electrically conductive layers vary with a vertical distance from a horizontal plane including a bottommost surface of the alternating stack (e.g., Fig. 12);
a vertical stack of memory elements (e.g., 250, Fig. 14, [206]) vertically extending through the alternating stack, wherein the memory elements are located at levels of the electrically conductive layers (e.g., Fig. 14); and
a contact assembly (e.g., 20 in 200, Fig. 16; Fig. 12; Fig. 14; 20 (17, 27, 37) in 200 includes the same structure/configuration/material as 55 (57, 67, 77) in 100 ([213]), thus, Fig. 14 depicting 55 is used in rejection) comprising:
a layer contact via structure (e.g., 179 and 173 of 27, Fig. 14, [175]) comprising an upper portion (e.g., 179, Fig. 14) and a lower portion (e.g., 173, Fig. 14) having a smaller width than the upper portion, wherein the upper portion (e.g., 179, Fig. 14) contacts a sidewall of an opening through a first electrically conductive layer (e.g., upper-most 346, Fig. 14) of the electrically conductive layers in the staircase region, and the lower portion (e.g., 173, Fig. 14) extends below the first electrically conductive layer (e.g., upper-most 346, Fig. 14); and
a dielectric base (e.g., 178, 174, Fig. 14, [173]) comprising a dielectric material and contacting an additional electrically conductive layer (e.g., lower-most 346, Fig. 14) of the electrically conductive layers, wherein the additional electrically conductive layer underlies the first electrically conductive layer (e.g., Fig. 14).
Regarding claim 2, Costa teaches the memory device of Claim 1, further comprising: a memory opening (e.g., 249, Fig. 11) vertically extending through the alternating stack; and a memory opening fill structure (e.g., 77, Fig. 14B, [213]) located in the memory opening, wherein the memory opening fill structure comprises a vertical semiconductor channel (e.g., 62, Fig. 14, [213]) and a memory film (e.g., 250, Fig. 14, [213]) wherein the memory elements comprise portions of the memory film located at the levels of the electrically conductive layers (e.g., Fig. 14).
Regarding claim 3, Costa teaches the memory device of Claim 2, wherein the layer contact via structure further comprises a horizontal step located between the upper portion and the lower portion (e.g., horizontal step between 179 and 173, Fig. 14).
Regarding claim 4, Costa teaches the memory device of Claim 3, wherein: wherein a cylindrical sidewall surface segment of the upper portion of the layer contact via structure contacts a cylindrical sidewall surface of the opening in the first electrically conductive layer (e.g., Figs. 6-7); and the lower portion contacts a first cylindrical sidewall surface segment of a cylindrical opening through a first insulating layer (e.g., 176, Fig. 14) of the insulating layers which overlies the additional electrically conductive layer and underlies the first electrically conductive layer (e.g., Figs. 6-7; Fig. 14).
Regarding claim 5, Costa teaches the memory device of Claim 4, wherein the dielectric base comprises a cylindrical sidewall surface segment that contacts a second cylindrical sidewall surface segment of the cylindrical opening through the first insulating layer (e.g., Figs. 6-7; Fig. 14).
Regarding claim 15, Costa teaches the memory device of Claim 1, further comprising a retro-stepped dielectric material portion (e.g., 265, Fig. 16) overlying the staircase region of the alternating stack and having a stepped bottom surface that contains horizontally-extending surface segments that are vertically offset from each other and adjoined to each other by vertically-extending surface segments (e.g., Fig. 16; Fig. 9), wherein the layer contact via structure vertically extending through an opening in one of the horizontally-extending surface segments (e.g., Fig. 16).
Allowable Subject Matter
Claims 6-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16 and 17 are allowed at this time, pending updated search before the Examiner's next response, because the prior art of record neither anticipates nor render obvious the limitation of the base claim 16 that recites “forming a layer contact via cavity through the retro-stepped dielectric material portion such that the layer contact via cavity vertically extends through a horizontally-extending surface segment of a stepped bottom surface of the retro-stepped dielectric material portion and through a first electrically conductive layer of the electrically conductive layers; forming a sacrificial tubular spacer in a peripheral volume of the layer contact via cavity; vertically extending the layer contact via cavity, wherein a vertically-extended portion of the layer contact via cavity extends at least through a first insulating layer of the insulating layers and into a second electrically conductive layer of the electrically conductive layers which underlies the first electrically conductive layer; performing a first isotropic etch process that etches a material of the electrically conductive layers selective to a material of the insulating layers to form a first fin cavity in a volume from which an annular portion of the second electrically conductive layer is removed; forming a dielectric base within a volume of the first fin cavity and a portion of the vertically-extended portion of the layer contact via cavity; and forming a layer contact via structure over the dielectric base on a physically exposed surface of the first electrically conductive layer” in combination with other elements of the base claim 16.
Claims 18-20 would be allowable if amended to overcome the claim objection stated above.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention.
For example, Wang US 2021/0091106, Hwang et al. US 2011/0151667 and Kidoh et al. US 2009/0224309 relate to a memory device including a staircase region of an alternating stack of insulating layers and electrically conductive layers as a contact region, and a vertical stack of memory elements vertically extending through the alternating stack as a memory region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 July 21, 2026
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