DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: Claim 5 recites “an insulating layer covering said silicon-based semiconductor device and said silicon substrate excepting said first area. . . .” It is believed “excepting” is a typo and instead should be “except.”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 1-4, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20200295045 (Lee et al).
Concerning claim 1, Lee discloses an integrated semiconductor structure comprising (Figs. 2A-3A):
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a silicon substrate (201+203+205) having a first area (21) and a second area (22), said first area being formed with a trench that has a trench surface (201) with a (111) orientation ([0033]), said second area having an area surface (205) with a (100) orientation ([0033]); a silicon-based semiconductor device (108) disposed on said area surface with the (100) orientation of said second area ([0018]); and a nitride-based semiconductor device (102) disposed on said trench surface with the (111) orientation of said trench ([0018]).
Continuing to claim 2, Lee discloses wherein said nitride-based semiconductor device includes a nitride-based heterojunction ([0018], note that the nitride device that is formed in the first area is a HEMT (high electron mobility transistor) which is a type of field effect transistor that uses a heterojunction as the channel instead of the doped region found in conventional MOSFETs).
Considering claim 3, Lee discloses further comprising a protection layer (300) covering said silicon-based semiconductor device and said nitride-based semiconductor device, and having a flat upper surface (Fig. 3A).
Referring to claim 4, Lee discloses
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further comprising: a first interconnecting metallic structure (rectangular region in annotated Fig. 3A above) that extends from said flat upper surface of said protection layer to said nitride-based semiconductor device to be electrically connected with said nitride-based semiconductor device ([0049]); and a second interconnecting metallic structure (oval region in annotated Fig. 3A above) that extends from said flat upper surface of said protection layer to said silicon-based semiconductor device to be electrically connected with said silicon-based semiconductor device ([0049]).
Regarding claim 7, Lee discloses wherein said silicon-based semiconductor device includes a semiconductor component or a circuit structure ([0045]).
Claim(s) 1, 2, 6-11, 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20150206796 (Dasgupta et al).
Pertaining to claim 1, Dasgupta discloses an integrated semiconductor structure comprising (Figs. 1 and 3A-3E, note that Fig. 1 is referenced to show that the electronic device structure (300) in the embodiment shown in Figs. 3A-3E has a Si CMOS portion (102) and a III-N portion (103) similar to Fig. 1 and Figs. 3A-3E shows the fabrication of the III-N portions of the electronic device [0052]): a silicon substrate (301) having a first area (103) and a second area (102), said first area being formed with a trench that has a trench surface (303 and 304) with a (111) orientation ([0098]), said second area having an area surface with a (100) orientation ([0098]); a silicon-based semiconductor device (102) disposed on said area surface with the (100) orientation of said second area ([0052] and [0098], note that the substrate is a Si substrate with a (100) orientation and therefore the surface that the silicon based semiconductor is formed on is the (100) surface of the Si substrate); and a nitride-based semiconductor device (103) disposed on said trench surface with the (111) orientation of said trench ([0098] and [0107]).
As to claim 2, Dasgupta discloses wherein said nitride-based semiconductor device includes a nitride-based heterojunction ([0107]).
Concerning claim 6, Dasgupta discloses wherein: said nitride-based semiconductor device further includes a nucleation layer (331) and an electrode structure ([0085] and [0107], Fig. 2K features 295-297, note that the contacts that are formed over the structure of Fig. 2K are described as also being formed over the device layer in the embodiment as seen in Fig. 3E) ; said nucleation layer is disposed in and fills said trench and is formed with a flat surface (Fig. 3C and [0099]), said nitride-based heterojunction being disposed on said flat surface ([0099]).
Continuing to claim 7, Dasgupta discloses wherein said silicon-based semiconductor device includes a semiconductor component or a circuit structure ([0052]).
Considering claim 8, Dasgupta discloses wherein said integrated semiconductor structure includes a plurality of said trenches formed contiguously in said first area (Fig. 3B and [0097]).
Referring to claims 9 and 10, Dasgupta discloses wherein each of said trenches has a trench depth (h) and an opening that has a width (c), and said trench surface of each of said trenches is inclined with respect to a horizontal reference plane at an inclined angle (a), wherein c/h = 1/(2 tan(α)), and said inclined angle (a) ranges from 54.5° to 54.9° and wherein said width (c) of said opening is 1.43 times said trench depth (h), and said inclined angle (a) is 54.7° ([0098] and Fig. 3B, note that the initial width of the trench (c) is a distance 309 between the trench sidewall blocks. In an embodiment, distance 309 in an approximate range from about 50 nm to about 1 .mu.m. In an embodiment, the depth 311 (h) is in an approximate range from about 35 nm to about 700 nm. The examiner is relying on the lower end of the ranges such that the width is 50 nm and the depth is 35 nm making the width 1.43 (1.4286) times the depth and corresponding to an angle of 54.7).
Regarding claim 11, Dasgupta discloses wherein said trench depth (h) ranges from 20 nm to 100 nm ([0098]).
Pertaining to claim 14, Dasgupta discloses wherein a thickness of said nucleation layer is no less than a trench depth (h) of said trench (Fig. 3C and [0099]).
As to claim 15, Dasgupta discloses wherein said nitride-based heterojunction includes a buffer layer (342 +343), a channel layer (332), and a barrier layer (334) ([0105]-[0107], note that buffer layers 342 and 343 are vertically grown on the nucleation layer using a selective area epitaxy. GaN is grown on top of the nucleation layer. Once the III-N material layer is grown out of the V-shaped trench, and then III-N material layer is laterally overgrown by changing growth parameters (e.g., temperature, pressure, surfactants, or any combination thereof) to form coalesced island, as described above with respect to type A trench. III-N material layer 332 represents one of the III-N material layers and is laterally grown over the trench sidewall blocks to form coalesced lateral epitaxial overgrowth ("LEO") islands, such as coalesced LEO islands 345, 346, and 347. Subsequently, capping layer 334 is deposited to enhance mobility in a two-dimensional electron gas ("2DEG") portion 333 (channel region) of the III-N material layer 332.)
Concerning claim 16, Dasgupta discloses wherein: said channel layer is made of one of GaN and AlxGa₁-xN; and said barrier layer is made of one of AIN, InN, AlxGa1-xN, InxAl₁-xN, and InxAlyGaN ([0094], [0105] and [0107], note that the capping layer material of Fig. 2N is disclosed as being the same as the capping layer material of Fig. 3E).
Continuing to claim 17, Dasgupta discloses a method for making an integrated semiconductor structure comprising (Figs. 1 and 3A-3E, note that Fig. 1 is referenced to show that the electronic device structure (300) in the embodiment shown in Figs. 3A-3E has a Si CMOS portion (102) and a III-N portion (103) similar to Fig. 1 and Figs. 3A-3E shows the fabrication of the III-N portions of the electronic device [0052]): a) providing a silicon substrate (301) having a first area and a second area each having an area surface with a (100) orientation ([0052] and [0098], note that the substrate is a Si substrate with a (100) orientation and therefore the surface that the silicon based semiconductor is formed on is the (100) surface of the Si substrate); b) forming a silicon-based semiconductor device on the area surface with the (100) orientation of the second area (Fig. 1 feature 102 and [0052]) ; c) wet etching the first area of the silicon substrate to form a trench having a trench surface with a (111) orientation([0098] and Fig. 3B); and d) forming a nitride-based semiconductor device on the trench surface to create a device preform (Fig. 3E and [0105]-[0107]).
Considering claim 19, Dasgupta discloses wherein the step d) of forming the nitride-based semiconductor device includes: d1) epitaxially growing a nucleation layer (331) in the trench to cover the trench (V) and form a flat surface ([0099], [0101], and [0102]); and d2) forming a nitride-based heterojunction and an electrode structure on the flat surface of the nucleation layer to form the nitride-based semiconductor device (Fig. 3E and [0105]-[0107]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5, 12, 13, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150206796 (Dasgupta et al) as applied to claims 1 and 17 above, and further in view of US 20210118724 (Walke et al).
Referring to claim 3, Dasgupta discloses forming a III-N(V) device and a Si device on a substrate (Figs. 3A-3E).
Dasgupta does not disclose a protection layer covering said silicon-based semiconductor device and said nitride-based semiconductor device, and having a flat upper surface. However, Walke discloses a method of forming a Si-based device in a second region (50) and a III-V based device (note that III-N is a III-V based device and therefore the disclosures are analogous) wherein a Si-based device is covered with a protective layer (55) while a V-shaped trench is formed in the III-V region (Fig. 5) followed by the formation of a III-V device (Fig. 7) that is then covered by another protective layer (90) both of which have flat upper surfaces. The protective layer is subsequently etched to provide access for later formed interconnects (91) ([0089]-[0091]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Dasgupta to include the formation of the protective layer and interconnect structure of Walke in order to provide electrical connection of these structures within the device.
Regarding claim 5, Dasgupta in view of Walke disclose wherein said protection layer includes: an insulating layer (Walke 55) covering said silicon-based semiconductor device and said silicon substrate except said first area (Walke Fig. 5); and a passivation layer (Walke 90) covering said insulating layer and said nitride-based semiconductor device (Walke Fig. 7).
Pertaining to claim 12, Dasgupta in view of Walke disclose wherein said insulating layer is made of silicon oxide (Walke [0091]).
As to claim 13, Dasgupta in view of Walke discloses wherein said passivation layer is made of one of silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride, or an organic insulating material (Walke [0091]).
Concerning claims 18 and 20, Dasgupta discloses wet etching the exposed first area of the silicon substrate to form the trench (V) having the trench surface with the (111) orientation ([0098]).
Dasgupta does not disclose wherein the step c) of wet etching the first area includes: c1) forming an insulating layer on the silicon substrate to cover the first area (A) and the silicon-based semiconductor device on the second area; c2) patterning the insulating layer to expose the first area of the silicon substrate; and further comprising, after the step d): e) forming a passivation layer on the device preform that covers the silicon-based semiconductor device and the nitride-based semiconductor device; f) planarizing the passivation layer to form a flat upper surface; g) etching the passivation layer to form a first interconnecting hole unit and a second interconnecting hole unit each of which extends from the flat upper surface of the passivation layer to respectively reach the nitride-based semiconductor device and the silicon-based semiconductor device; h) forming a first interconnecting metallic structure and a second interconnecting metallic structure that are electrically connected to each other, the first interconnecting metallic structure and the second interconnecting metallic structure respectively extending into the first interconnecting hole and the second interconnecting hole to be electrically connected to the nitride-based semiconductor device and the silicon-based semiconductor device, respectively. However, Walke discloses a method of forming a Si-based device in a second region (50) and a III-V based device (note that III-N is a III-V based device and therefore the disclosures are analogous) wherein a Si-based device is covered with a protective layer (55) while a V-shaped trench is formed in the III-V region (Fig. 5) followed by the formation of a III-V device (Fig. 7) that is then covered by another protective layer (90) both of which have flat upper surfaces. The protective layer is subsequently etched to provide access for later formed interconnects (91) ([0089]-[0091]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Dasgupta to include the formation of the protective layer and interconnect structure of Walke in order to provide electrical connection of these structures within the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 9343569 (Fig 16 and Abstract) and US 20110108850 (Fig. 3d and [0069]-[0072]) disclose Si based and III-N based devices formed on Si (100) substrates that have been etched to provide Si (111) surfaces for III-N devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 06/09/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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